| Device Utilization Summary | [-] |
| Slice Logic Utilization | Used | Available | Utilization | Note(s) |
| Number of Slice Registers |
3,660 |
11,440 |
31% |
|
| Number used as Flip Flops |
3,651 |
|
|
|
| Number used as Latches |
1 |
|
|
|
| Number used as Latch-thrus |
0 |
|
|
|
| Number used as AND/OR logics |
8 |
|
|
|
| Number of Slice LUTs |
4,639 |
5,720 |
81% |
|
| Number used as logic |
4,251 |
5,720 |
74% |
|
| Number using O6 output only |
3,278 |
|
|
|
| Number using O5 output only |
68 |
|
|
|
| Number using O5 and O6 |
905 |
|
|
|
| Number used as ROM |
0 |
|
|
|
| Number used as Memory |
274 |
1,440 |
19% |
|
| Number used as Dual Port RAM |
88 |
|
|
|
| Number using O6 output only |
4 |
|
|
|
| Number using O5 output only |
0 |
|
|
|
| Number using O5 and O6 |
84 |
|
|
|
| Number used as Single Port RAM |
0 |
|
|
|
| Number used as Shift Register |
186 |
|
|
|
| Number using O6 output only |
45 |
|
|
|
| Number using O5 output only |
1 |
|
|
|
| Number using O5 and O6 |
140 |
|
|
|
| Number used exclusively as route-thrus |
114 |
|
|
|
| Number with same-slice register load |
99 |
|
|
|
| Number with same-slice carry load |
15 |
|
|
|
| Number with other load |
0 |
|
|
|
| Number of occupied Slices |
1,429 |
1,430 |
99% |
|
| Nummber of MUXCYs used |
572 |
2,860 |
20% |
|
| Number of LUT Flip Flop pairs used |
5,035 |
|
|
|
| Number with an unused Flip Flop |
1,750 |
5,035 |
34% |
|
| Number with an unused LUT |
396 |
5,035 |
7% |
|
| Number of fully used LUT-FF pairs |
2,889 |
5,035 |
57% |
|
| Number of unique control sets |
320 |
|
|
|
Number of slice register sites lost
to control set restrictions |
1,194 |
11,440 |
10% |
|
| Number of bonded IOBs |
78 |
200 |
39% |
|
| Number of LOCed IOBs |
78 |
78 |
100% |
|
| IOB Flip Flops |
6 |
|
|
|
| Number of RAMB16BWERs |
14 |
32 |
43% |
|
| Number of RAMB8BWERs |
0 |
64 |
0% |
|
| Number of BUFIO2/BUFIO2_2CLKs |
1 |
32 |
3% |
|
| Number used as BUFIO2s |
1 |
|
|
|
| Number used as BUFIO2_2CLKs |
0 |
|
|
|
| Number of BUFIO2FB/BUFIO2FB_2CLKs |
0 |
32 |
0% |
|
| Number of BUFG/BUFGMUXs |
2 |
16 |
12% |
|
| Number used as BUFGs |
2 |
|
|
|
| Number used as BUFGMUX |
0 |
|
|
|
| Number of DCM/DCM_CLKGENs |
0 |
4 |
0% |
|
| Number of ILOGIC2/ISERDES2s |
3 |
200 |
1% |
|
| Number used as ILOGIC2s |
3 |
|
|
|
| Number used as ISERDES2s |
0 |
|
|
|
| Number of IODELAY2/IODRP2/IODRP2_MCBs |
23 |
200 |
11% |
|
| Number used as IODELAY2s |
0 |
|
|
|
| Number used as IODRP2s |
1 |
|
|
|
| Number used as IODRP2_MCBs |
22 |
|
|
|
| Number of OLOGIC2/OSERDES2s |
46 |
200 |
23% |
|
| Number used as OLOGIC2s |
3 |
|
|
|
| Number used as OSERDES2s |
43 |
|
|
|
| Number of BSCANs |
1 |
4 |
25% |
|
| Number of BUFHs |
0 |
128 |
0% |
|
| Number of BUFPLLs |
0 |
8 |
0% |
|
| Number of BUFPLL_MCBs |
1 |
4 |
25% |
|
| Number of DSP48A1s |
3 |
16 |
18% |
|
| Number of ICAPs |
0 |
1 |
0% |
|
| Number of MCBs |
1 |
2 |
50% |
|
| Number of PCILOGICSEs |
0 |
2 |
0% |
|
| Number of PLL_ADVs |
1 |
2 |
50% |
|
| Number of PMVs |
0 |
1 |
0% |
|
| Number of STARTUPs |
0 |
1 |
0% |
|
| Number of SUSPEND_SYNCs |
0 |
1 |
0% |
|
| Average Fanout of Non-Clock Nets |
3.92 |
|
|
|