maximDeviceSpecificUtilities.c

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/*
 * Copyright (C) 2012 Maxim Integrated Products, Inc., All Rights Reserved.
 *
 * Permission is hereby granted, free of charge, to any person obtaining a
 * copy of this software and associated documentation files (the "Software"),
 * to deal in the Software without restriction, including without limitation
 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
 * and/or sell copies of the Software, and to permit persons to whom the
 * Software is furnished to do so, subject to the following conditions:
 *
 * The above copyright notice and this permission notice shall be included
 * in all copies or substantial portions of the Software.
 *
 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
 * MERCHANTABILITY,  FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
 * IN NO EVENT SHALL MAXIM INTEGRATED PRODUCTS BE LIABLE FOR ANY CLAIM, DAMAGES
 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
 * OTHER DEALINGS IN THE SOFTWARE.
 *
 * Except as contained in this notice, the name of Maxim Integrated Products
 * shall not be used except as stated in the Maxim Integrated Products
 * Branding Policy.
 *
 * The mere transfer of this software does not imply any licenses
 * of trade secrets, proprietary technology, copyrights, patents,
 * trademarks, maskwork rights, or any other form of intellectual
 * property whatsoever. Maxim Integrated Products retains all ownership rights.
 *
 ***************************************************************************/

#include "xbasic_types.h"
#include "stdio.h"
#include "maximDeviceSpecificUtilities.h"
#include "utilities.h"


u32 read_reg(u8 uchRegAddr)
{
    u8 uchRegValue[3];
    u8 uchSPIWBuffer[2];

    //preparing read command
    uchSPIWBuffer[0] = uchRegAddr>>6;
    uchSPIWBuffer[0] = (uchSPIWBuffer[0]<<2)+1;
    uchSPIWBuffer[1] = 0x3F & uchRegAddr;
    uchSPIWBuffer[1] = uchSPIWBuffer[1]<<2;

    /* Write to the control register:
     * MSB first
     * Master transctions inhibit
     * Slave select output follows data in slave select regitster
     * Rx and Tx FIFO normal operation
     * CPHA = CPOL = 1
     * SPI master mode
     * SPI system enabled
     * Normal operation
     */
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x60, 0x19E);

    //CS high
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x70, 0xFFFFFFFF);

    //CS low
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x70, 0xFFFFFFFE);

    //Write 3 bytes to Tx FIFO
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x68, uchSPIWBuffer[0]);
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x68, uchSPIWBuffer[1]);
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x68, 0x00);
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x68, 0x00);
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x68, 0x00);

    //Un-inhibit our SPI master to transfer the data
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x60, 0x09E);

    //Wait for transaction to complete.  Check to see if Tx_Empty flag is set before proceeding.
    while( !(XSpi_ReadReg( XPAR_SPI_0_BASEADDR, 0x64 ) & 0x00000004) );

    //CS high
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x70, 0xFFFFFFFF);

    //Inhibit SPI master to prevent further action
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x60, 0x19E);

    //Read a value from the Rx FIFO
    uchRegValue[0]=XSpi_ReadReg(XPAR_SPI_0_BASEADDR, 0x6C);
    //Read a value from the Rx FIFO
    uchRegValue[0]=XSpi_ReadReg(XPAR_SPI_0_BASEADDR, 0x6C);
    //Read a value from the Rx FIFO
    uchRegValue[0]=XSpi_ReadReg(XPAR_SPI_0_BASEADDR, 0x6C);
    //Read a value from the Rx FIFO
    uchRegValue[1]=XSpi_ReadReg(XPAR_SPI_0_BASEADDR, 0x6C);
    //Read a value from the Rx FIFO
    uchRegValue[2]=XSpi_ReadReg(XPAR_SPI_0_BASEADDR, 0x6C);

    return (uchRegValue[0]<<16) + (uchRegValue[1]<<8) + uchRegValue[2];

}

void write_reg(u8 uchRegAddr, u32 unRegValue)
{
    u8 uchSPIWBuffer[5];
    u8 uchDummy;

    //preparing write command
    uchSPIWBuffer[0] = uchRegAddr>>6;
    uchSPIWBuffer[0] = (uchSPIWBuffer[0]<<2)+1;
    uchSPIWBuffer[1] = 0x3F & uchRegAddr;
    uchSPIWBuffer[1] = (uchSPIWBuffer[1]<<2)+2;
    uchSPIWBuffer[2] = unRegValue>>16;
    uchSPIWBuffer[3] = unRegValue>>8;
    uchSPIWBuffer[4] = unRegValue;

    /* Write to the control register:
     * MSB first
     * Master transctions inhibit
     * Slave select output follows data in slave select regitster
     * Rx and Tx FIFO normal operation
     * CPHA = CPOL = 1
     * SPI master mode
     * SPI system enabled
     * Normal operation
     */
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x60, 0x19E);

    //CS high
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x70, 0xFFFFFFFF);

    //CS low
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x70, 0xFFFFFFFE);

    //Write 3 bytes to Tx FIFO
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x68, uchSPIWBuffer[0]);
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x68, uchSPIWBuffer[1]);
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x68, uchSPIWBuffer[2]);
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x68, uchSPIWBuffer[3]);
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x68, uchSPIWBuffer[4]);

    //Un-inhibit our SPI master to transfer the data
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x60, 0x09E);

    //Wait for transaction to complete.  Check to see if Tx_Empty flag is set before proceeding.
    while( !(XSpi_ReadReg( XPAR_SPI_0_BASEADDR, 0x64 ) & 0x00000004) );

    //CS high
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x70, 0xFFFFFFFF);

    //Inhibit SPI master to prevent further action
    XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x60, 0x19E);

    //Read a value from the Rx FIFO
    uchDummy=XSpi_ReadReg(XPAR_SPI_0_BASEADDR, 0x6C);
    //Read a value from the Rx FIFO
    uchDummy=XSpi_ReadReg(XPAR_SPI_0_BASEADDR, 0x6C);
    //Read a value from the Rx FIFO
    uchDummy=XSpi_ReadReg(XPAR_SPI_0_BASEADDR, 0x6C);
    //Read a value from the Rx FIFO
    uchDummy=XSpi_ReadReg(XPAR_SPI_0_BASEADDR, 0x6C);
    //Read a value from the Rx FIFO
    uchDummy=XSpi_ReadReg(XPAR_SPI_0_BASEADDR, 0x6C);

}