topLevel Project Status (06/13/2013 - 13:21:39)
Project File: | top.xise | Parser Errors: | No Errors
Module Name: | topLevel | Implementation State: | Programming File Generated
Target Device: | xc6slx9-2csg324 | Errors: | No Errors
Product Version: | ISE 13.4 | Warnings: | 153 Warnings (0 new)
Design Goal: | Balanced | Routing Results: | All Signals Completely Routed
Design Strategy: | Xilinx Default (unlocked) | Timing Constraints: | All Constraints Met
Environment: | System Settings | Final Timing Score: | 0 (Timing Report)

XPS Reports | [-]
Report Name | Generated | Errors | Warnings | Infos
Platgen Log File | Thu Jun 13 13:09:48 2013 | 0 | 9 Warnings (1 new) | 28 Infos (0 new)
Simgen Log File |  |  |  |
BitInit Log File | Thu Jun 13 13:21:38 2013 | 0 | 0 | 11 Infos (0 new)
System Log File |  |  |  |

Device Utilization Summary | [-]
Slice Logic Utilization | Used | Available | Utilization | Note(s)
Number of Slice Registers | 3,660 | 11,440 | 31% |
Number used as Flip Flops | 3,651 |  |  |
Number used as Latches | 1 |  |  |
Number used as Latch-thrus | 0 |  |  |
Number used as AND/OR logics | 8 |  |  |
Number of Slice LUTs | 4,639 | 5,720 | 81% |
Number used as logic | 4,251 | 5,720 | 74% |
Number using O6 output only | 3,278 |  |  |
Number using O5 output only | 68 |  |  |
Number using O5 and O6 | 905 |  |  |
Number used as ROM | 0 |  |  |
Number used as Memory | 274 | 1,440 | 19% |
Number used as Dual Port RAM | 88 |  |  |
Number using O6 output only | 4 |  |  |
Number using O5 output only | 0 |  |  |
Number using O5 and O6 | 84 |  |  |
Number used as Single Port RAM | 0 |  |  |
Number used as Shift Register | 186 |  |  |
Number using O6 output only | 45 |  |  |
Number using O5 output only | 1 |  |  |
Number using O5 and O6 | 140 |  |  |
Number used exclusively as route-thrus | 114 |  |  |
Number with same-slice register load | 99 |  |  |
Number with same-slice carry load | 15 |  |  |
Number with other load | 0 |  |  |
Number of occupied Slices | 1,429 | 1,430 | 99% |
Nummber of MUXCYs used | 572 | 2,860 | 20% |
Number of LUT Flip Flop pairs used | 5,035 |  |  |
Number with an unused Flip Flop | 1,750 | 5,035 | 34% |
Number with an unused LUT | 396 | 5,035 | 7% |
Number of fully used LUT-FF pairs | 2,889 | 5,035 | 57% |
Number of unique control sets | 320 |  |  |
Number of slice register sites lost to control set restrictions | 1,194 | 11,440 | 10% |
Number of bonded IOBs | 78 | 200 | 39% |
Number of LOCed IOBs | 78 | 78 | 100% |
IOB Flip Flops | 6 |  |  |
Number of RAMB16BWERs | 14 | 32 | 43% |
Number of RAMB8BWERs | 0 | 64 | 0% |
Number of BUFIO2/BUFIO2_2CLKs | 1 | 32 | 3% |
Number used as BUFIO2s | 1 |  |  |
Number used as BUFIO2_2CLKs | 0 |  |  |
Number of BUFIO2FB/BUFIO2FB_2CLKs | 0 | 32 | 0% |
Number of BUFG/BUFGMUXs | 2 | 16 | 12% |
Number used as BUFGs | 2 |  |  |
Number used as BUFGMUX | 0 |  |  |
Number of DCM/DCM_CLKGENs | 0 | 4 | 0% |
Number of ILOGIC2/ISERDES2s | 3 | 200 | 1% |
Number used as ILOGIC2s | 3 |  |  |
Number used as ISERDES2s | 0 |  |  |
Number of IODELAY2/IODRP2/IODRP2_MCBs | 23 | 200 | 11% |
Number used as IODELAY2s | 0 |  |  |
Number used as IODRP2s | 1 |  |  |
Number used as IODRP2_MCBs | 22 |  |  |
Number of OLOGIC2/OSERDES2s | 46 | 200 | 23% |
Number used as OLOGIC2s | 3 |  |  |
Number used as OSERDES2s | 43 |  |  |
Number of BSCANs | 1 | 4 | 25% |
Number of BUFHs | 0 | 128 | 0% |
Number of BUFPLLs | 0 | 8 | 0% |
Number of BUFPLL_MCBs | 1 | 4 | 25% |
Number of DSP48A1s | 3 | 16 | 18% |
Number of ICAPs | 0 | 1 | 0% |
Number of MCBs | 1 | 2 | 50% |
Number of PCILOGICSEs | 0 | 2 | 0% |
Number of PLL_ADVs | 1 | 2 | 50% |
Number of PMVs | 0 | 1 | 0% |
Number of STARTUPs | 0 | 1 | 0% |
Number of SUSPEND_SYNCs | 0 | 1 | 0% |
Average Fanout of Non-Clock Nets | 3.92 |  |  |

Performance Summary | [-]
Final Timing Score: | 0 (Setup: 0, Hold: 0, Component Switching Limit: 0) | Pinout Data: | Pinout Report
Routing Results: | All Signals Completely Routed | Clock Data: | Clock Report
Timing Constraints: | All Constraints Met |  |

Detailed Reports | [-]
Report Name | Status | Generated | Errors | Warnings | Infos
Synthesis Report | Current | Fri Jul 20 13:57:18 2012 | 0 | 47 Warnings (0 new) | 808 Infos (750 new)
Translation Report | Current | Thu Jun 13 13:16:01 2013 | 0 | 32 Warnings (0 new) | 3 Infos (0 new)
Map Report | Current | Thu Jun 13 13:18:59 2013 | 0 | 24 Warnings (0 new) | 10 Infos (0 new)
Place and Route Report | Current | Thu Jun 13 13:20:09 2013 | 0 | 26 Warnings (0 new) | 2 Infos (0 new)
Power Report |  |  |  |  |
Post-PAR Static Timing Report | Current | Thu Jun 13 13:20:32 2013 | 0 | 1 Warning (0 new) | 4 Infos (0 new)
Bitgen Report | Current | Thu Jun 13 13:21:13 2013 | 0 | 23 Warnings (0 new) | 0

Secondary Reports | [-]
Report Name | Status | Generated
WebTalk Report | Current | Thu Jun 13 13:21:14 2013
WebTalk Log File | Current | Thu Jun 13 13:21:25 2013

Date Generated: 06/13/2013 - 13:21:39