
/*******************************************************************
*
* CAUTION: This file is automatically generated by libgen.
* Version: Xilinx EDK 14.2 EDK_P.28xd
* DO NOT EDIT.
*
* Copyright (c) 1995-2012 Xilinx, Inc.  All rights reserved.

* 
* Description: Driver parameters
*
*******************************************************************/

#include "xparameters_ps.h"

#define STDIN_BASEADDRESS 0xE0001000
#define STDOUT_BASEADDRESS 0xE0001000

/******************************************************************/

/* Definitions for driver GPIO */
#define XPAR_XGPIO_NUM_INSTANCES 2

/* Definitions for peripheral AXI_GPIO_LED */
#define XPAR_AXI_GPIO_LED_BASEADDR 0x41220000
#define XPAR_AXI_GPIO_LED_HIGHADDR 0x4122FFFF
#define XPAR_AXI_GPIO_LED_DEVICE_ID 0
#define XPAR_AXI_GPIO_LED_INTERRUPT_PRESENT 0
#define XPAR_AXI_GPIO_LED_IS_DUAL 0


/* Definitions for peripheral AXI_GPIO_OLED */
#define XPAR_AXI_GPIO_OLED_BASEADDR 0x41200000
#define XPAR_AXI_GPIO_OLED_HIGHADDR 0x4120FFFF
#define XPAR_AXI_GPIO_OLED_DEVICE_ID 1
#define XPAR_AXI_GPIO_OLED_INTERRUPT_PRESENT 0
#define XPAR_AXI_GPIO_OLED_IS_DUAL 0


/******************************************************************/


/* Definitions for peripheral PS7_DDR_0 */
#define XPAR_PS7_DDR_0_S_AXI_BASEADDR 0x00100000
#define XPAR_PS7_DDR_0_S_AXI_HIGHADDR 0x1FFFFFFF
#define XPAR_PS7_DDR_0_S_AXI_HP0_BASEADDR 0x00000000
#define XPAR_PS7_DDR_0_S_AXI_HP0_HIGHADDR 0x3FFFFFFF
#define XPAR_PS7_DDR_0_S_AXI_HP1_BASEADDR 0x00000000
#define XPAR_PS7_DDR_0_S_AXI_HP1_HIGHADDR 0x3FFFFFFF
#define XPAR_PS7_DDR_0_S_AXI_HP2_BASEADDR 0x00000000
#define XPAR_PS7_DDR_0_S_AXI_HP2_HIGHADDR 0x3FFFFFFF
#define XPAR_PS7_DDR_0_S_AXI_HP3_BASEADDR 0x00000000
#define XPAR_PS7_DDR_0_S_AXI_HP3_HIGHADDR 0x3FFFFFFF


/* Definitions for peripheral PS7_DDRC_0 */
#define XPAR_PS7_DDRC_0_S_AXI_BASEADDR 0xF8006000
#define XPAR_PS7_DDRC_0_S_AXI_HIGHADDR 0xF8006FFF


/* Definitions for peripheral PS7_IOP_BUS_CONFIG_0 */
#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_BASEADDR 0xE0200000
#define XPAR_PS7_IOP_BUS_CONFIG_0_S_AXI_HIGHADDR 0xE0200FFF


/* Definitions for peripheral PS7_QSPI_LINEAR_0 */
#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_BASEADDR 0xFC000000
#define XPAR_PS7_QSPI_LINEAR_0_S_AXI_HIGHADDR 0xFCFFFFFF


/* Definitions for peripheral PS7_RAM_0 */
#define XPAR_PS7_RAM_0_S_AXI_BASEADDR 0x00000000
#define XPAR_PS7_RAM_0_S_AXI_HIGHADDR 0x0002FFFF
#define XPAR_PS7_RAM_0_S_AXI_HP0_HIGHOCM_BASEADDR 0xFFFC0000
#define XPAR_PS7_RAM_0_S_AXI_HP0_HIGHOCM_HIGHADDR 0xFFFFFDFF
#define XPAR_PS7_RAM_0_S_AXI_HP1_HIGHOCM_BASEADDR 0xFFFC0000
#define XPAR_PS7_RAM_0_S_AXI_HP1_HIGHOCM_HIGHADDR 0xFFFFFDFF
#define XPAR_PS7_RAM_0_S_AXI_HP2_HIGHOCM_BASEADDR 0xFFFC0000
#define XPAR_PS7_RAM_0_S_AXI_HP2_HIGHOCM_HIGHADDR 0xFFFFFDFF
#define XPAR_PS7_RAM_0_S_AXI_HP3_HIGHOCM_BASEADDR 0xFFFC0000
#define XPAR_PS7_RAM_0_S_AXI_HP3_HIGHOCM_HIGHADDR 0xFFFFFDFF


/* Definitions for peripheral PS7_RAM_1 */
#define XPAR_PS7_RAM_1_S_AXI_BASEADDR 0xFFFF0000
#define XPAR_PS7_RAM_1_S_AXI_HIGHADDR 0xFFFFFDFF
#define XPAR_PS7_RAM_1_S_AXI_HP0_HIGHOCM_BASEADDR 0xFFFC0000
#define XPAR_PS7_RAM_1_S_AXI_HP0_HIGHOCM_HIGHADDR 0xFFFFFDFF
#define XPAR_PS7_RAM_1_S_AXI_HP1_HIGHOCM_BASEADDR 0xFFFC0000
#define XPAR_PS7_RAM_1_S_AXI_HP1_HIGHOCM_HIGHADDR 0xFFFFFDFF
#define XPAR_PS7_RAM_1_S_AXI_HP2_HIGHOCM_BASEADDR 0xFFFC0000
#define XPAR_PS7_RAM_1_S_AXI_HP2_HIGHOCM_HIGHADDR 0xFFFFFDFF
#define XPAR_PS7_RAM_1_S_AXI_HP3_HIGHOCM_BASEADDR 0xFFFC0000
#define XPAR_PS7_RAM_1_S_AXI_HP3_HIGHOCM_HIGHADDR 0xFFFFFDFF


/* Definitions for peripheral PS7_SD_0 */
#define XPAR_PS7_SD_0_S_AXI_BASEADDR 0xE0100000
#define XPAR_PS7_SD_0_S_AXI_HIGHADDR 0xE0100FFF


/* Definitions for peripheral PS7_SLCR_0 */
#define XPAR_PS7_SLCR_0_S_AXI_BASEADDR 0xF8000000
#define XPAR_PS7_SLCR_0_S_AXI_HIGHADDR 0xF8000FFF


/******************************************************************/

/* Definitions for driver DEVCFG */
#define XPAR_XDCFG_NUM_INSTANCES 1

/* Definitions for peripheral PS7_DEV_CFG_0 */
#define XPAR_PS7_DEV_CFG_0_DEVICE_ID 0
#define XPAR_PS7_DEV_CFG_0_BASEADDR 0xF8007000
#define XPAR_PS7_DEV_CFG_0_HIGHADDR 0xF8007FFF


/******************************************************************/

/* Canonical definitions for peripheral PS7_DEV_CFG_0 */
#define XPAR_XDCFG_0_DEVICE_ID XPAR_PS7_DEV_CFG_0_DEVICE_ID
#define XPAR_XDCFG_0_BASEADDR 0xF8007000
#define XPAR_XDCFG_0_HIGHADDR 0xF8007FFF


/******************************************************************/

/* Definitions for driver DMAPS */
#define XPAR_XDMAPS_NUM_INSTANCES 2

/* Definitions for peripheral PS7_DMA_NS */
#define XPAR_PS7_DMA_NS_DEVICE_ID 0
#define XPAR_PS7_DMA_NS_BASEADDR 0xF8004000
#define XPAR_PS7_DMA_NS_HIGHADDR 0xF8004FFF


/* Definitions for peripheral PS7_DMA_S */
#define XPAR_PS7_DMA_S_DEVICE_ID 1
#define XPAR_PS7_DMA_S_BASEADDR 0xF8003000
#define XPAR_PS7_DMA_S_HIGHADDR 0xF8003FFF


/******************************************************************/

/* Canonical definitions for peripheral PS7_DMA_NS */
#define XPAR_XDMAPS_0_DEVICE_ID XPAR_PS7_DMA_NS_DEVICE_ID
#define XPAR_XDMAPS_0_BASEADDR 0xF8004000
#define XPAR_XDMAPS_0_HIGHADDR 0xF8004FFF

/* Canonical definitions for peripheral PS7_DMA_S */
#define XPAR_XDMAPS_1_DEVICE_ID XPAR_PS7_DMA_S_DEVICE_ID
#define XPAR_XDMAPS_1_BASEADDR 0xF8003000
#define XPAR_XDMAPS_1_HIGHADDR 0xF8003FFF


/******************************************************************/

/* Definitions for driver QSPIPS */
#define XPAR_XQSPIPS_NUM_INSTANCES 1

/* Definitions for peripheral PS7_QSPI_0 */
#define XPAR_PS7_QSPI_0_DEVICE_ID 0
#define XPAR_PS7_QSPI_0_BASEADDR 0xE000D000
#define XPAR_PS7_QSPI_0_HIGHADDR 0xE000DFFF
#define XPAR_PS7_QSPI_0_QSPI_CLK_FREQ_HZ 200000000


/******************************************************************/

/* Canonical definitions for peripheral PS7_QSPI_0 */
#define XPAR_XQSPIPS_0_DEVICE_ID XPAR_PS7_QSPI_0_DEVICE_ID
#define XPAR_XQSPIPS_0_BASEADDR 0xE000D000
#define XPAR_XQSPIPS_0_HIGHADDR 0xE000DFFF
#define XPAR_XQSPIPS_0_QSPI_CLK_FREQ_HZ 200000000


/******************************************************************/

/* Definitions for Fabric interrupts connected to ps7_scugic_0 */

/******************************************************************/

/* Canonical definitions for Fabric interrupts connected to ps7_scugic_0 */

/******************************************************************/

/* Definitions for driver SCUGIC */
#define XPAR_XSCUGIC_NUM_INSTANCES 1

/* Definitions for peripheral PS7_SCUGIC_0 */
#define XPAR_PS7_SCUGIC_0_DEVICE_ID 0
#define XPAR_PS7_SCUGIC_0_BASEADDR 0xF8F00100
#define XPAR_PS7_SCUGIC_0_HIGHADDR 0xF8F001FF
#define XPAR_PS7_SCUGIC_0_DIST_BASEADDR 0xF8F01000


/******************************************************************/

/* Canonical definitions for peripheral PS7_SCUGIC_0 */
#define XPAR_SCUGIC_0_DEVICE_ID XPAR_PS7_SCUGIC_0_DEVICE_ID
#define XPAR_SCUGIC_0_CPU_BASEADDR 0xF8F00100
#define XPAR_SCUGIC_0_CPU_HIGHADDR 0xF8F001FF
#define XPAR_SCUGIC_0_DIST_BASEADDR 0xF8F01000


/******************************************************************/

/* Definitions for driver SCUTIMER */
#define XPAR_XSCUTIMER_NUM_INSTANCES 1

/* Definitions for peripheral PS7_SCUTIMER_0 */
#define XPAR_PS7_SCUTIMER_0_DEVICE_ID 0
#define XPAR_PS7_SCUTIMER_0_BASEADDR 0xF8F00600
#define XPAR_PS7_SCUTIMER_0_HIGHADDR 0xF8F0061F


/******************************************************************/

/* Canonical definitions for peripheral PS7_SCUTIMER_0 */
#define XPAR_XSCUTIMER_0_DEVICE_ID XPAR_PS7_SCUTIMER_0_DEVICE_ID
#define XPAR_XSCUTIMER_0_BASEADDR 0xF8F00600
#define XPAR_XSCUTIMER_0_HIGHADDR 0xF8F0061F


/******************************************************************/

/* Definitions for driver SCUWDT */
#define XPAR_XSCUWDT_NUM_INSTANCES 1

/* Definitions for peripheral PS7_SCUWDT_0 */
#define XPAR_PS7_SCUWDT_0_DEVICE_ID 0
#define XPAR_PS7_SCUWDT_0_BASEADDR 0xF8F00620
#define XPAR_PS7_SCUWDT_0_HIGHADDR 0xF8F006FF


/******************************************************************/

/* Canonical definitions for peripheral PS7_SCUWDT_0 */
#define XPAR_SCUWDT_0_DEVICE_ID XPAR_PS7_SCUWDT_0_DEVICE_ID
#define XPAR_SCUWDT_0_BASEADDR 0xF8F00620
#define XPAR_SCUWDT_0_HIGHADDR 0xF8F006FF


/******************************************************************/

/* Definitions for driver SPIPS */
#define XPAR_XSPIPS_NUM_INSTANCES 1

/* Definitions for peripheral PS7_SPI_1 */
#define XPAR_PS7_SPI_1_DEVICE_ID 0
#define XPAR_PS7_SPI_1_BASEADDR 0xE0007000
#define XPAR_PS7_SPI_1_HIGHADDR 0xE0007FFF
#define XPAR_PS7_SPI_1_SPI_CLK_FREQ_HZ 166666666


/******************************************************************/

/* Canonical definitions for peripheral PS7_SPI_1 */
#define XPAR_XSPIPS_0_DEVICE_ID XPAR_PS7_SPI_1_DEVICE_ID
#define XPAR_XSPIPS_0_BASEADDR 0xE0007000
#define XPAR_XSPIPS_0_HIGHADDR 0xE0007FFF
#define XPAR_XSPIPS_0_SPI_CLK_FREQ_HZ 166666666


/******************************************************************/

/* Definitions for driver UARTPS */
#define XPAR_XUARTPS_NUM_INSTANCES 1

/* Definitions for peripheral PS7_UART_1 */
#define XPAR_PS7_UART_1_DEVICE_ID 0
#define XPAR_PS7_UART_1_BASEADDR 0xE0001000
#define XPAR_PS7_UART_1_HIGHADDR 0xE0001FFF
#define XPAR_PS7_UART_1_UART_CLK_FREQ_HZ 50000000
#define XPAR_PS7_UART_1_HAS_MODEM 0


/******************************************************************/

/* Canonical definitions for peripheral PS7_UART_1 */
#define XPAR_XUARTPS_0_DEVICE_ID XPAR_PS7_UART_1_DEVICE_ID
#define XPAR_XUARTPS_0_BASEADDR 0xE0001000
#define XPAR_XUARTPS_0_HIGHADDR 0xE0001FFF
#define XPAR_XUARTPS_0_UART_CLK_FREQ_HZ 50000000
#define XPAR_XUARTPS_0_HAS_MODEM 0


/******************************************************************/

/* Definition for CPU ID */
#define XPAR_CPU_ID 0

/* Definitions for peripheral PS7_CORTEXA9_0 */
#define XPAR_PS7_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687


/******************************************************************/

/* Canonical definitions for peripheral PS7_CORTEXA9_0 */
#define XPAR_CPU_CORTEXA9_0_CPU_CLK_FREQ_HZ 666666687


/******************************************************************/

