module system
	(
	rzq,
	mcbx_dram_we_n,
	mcbx_dram_udqs,
	mcbx_dram_udm,
	mcbx_dram_ras_n,
	mcbx_dram_ldm,
	mcbx_dram_dqs,
	mcbx_dram_dq,
	mcbx_dram_clk_n,
	mcbx_dram_clk,
	mcbx_dram_cke,
	mcbx_dram_cas_n,
	mcbx_dram_ba,
	mcbx_dram_addr,
	USB_Uart_sout,
	USB_Uart_sin,
	SPI_FLASH_Wn_net_vcc,
	SPI_FLASH_SS,
	SPI_FLASH_SCLK,
	SPI_FLASH_MOSI,
	SPI_FLASH_MISO,
	SPI_FLASH_HOLDn_net_vcc,
	RESET,
	LEDs_4Bits_TRI_O,
	DIP_Switches_4Bits_TRI_I,
	CLK_66MHZ,
	CDCE913_SDA,
	CDCE913_SCL,
	axi_uartlite_0_RX_pin,
	axi_uartlite_0_TX_pin,
	axi_spi_0_SCK_O_pin,
	axi_spi_0_SS_O_pin,
	axi_spi_0_MOSI_O_pin,
	axi_spi_0_MISO_I_pin,
	axi_gpio_0_GPIO_IO_I_pin,
	axi_gpio_0_GPIO_IO_O_pin,
	axi_gpio_0_GPIO_IO_T_pin,
	axi_iic_0_Sda_I_pin,
	axi_iic_0_Sda_O_pin,
	axi_iic_0_Sda_T_pin,
	axi_iic_0_Scl_I_pin,
	axi_iic_0_Scl_O_pin,
	axi_iic_0_Scl_T_pin,
	axi_gpio_2_GPIO_IO_I_pin,
	axi_gpio_2_GPIO_IO_O_pin,
	axi_gpio_2_GPIO_IO_T_pin,
	axi_gpio_1_GPIO_IO
	);
inout  rzq;
output  mcbx_dram_we_n;
inout  mcbx_dram_udqs;
output  mcbx_dram_udm;
output  mcbx_dram_ras_n;
output  mcbx_dram_ldm;
inout  mcbx_dram_dqs;
inout [15:0] mcbx_dram_dq;
output  mcbx_dram_clk_n;
output  mcbx_dram_clk;
output  mcbx_dram_cke;
output  mcbx_dram_cas_n;
output [1:0] mcbx_dram_ba;
output [12:0] mcbx_dram_addr;
output  USB_Uart_sout;
input  USB_Uart_sin;
output  SPI_FLASH_Wn_net_vcc;
inout  SPI_FLASH_SS;
inout  SPI_FLASH_SCLK;
inout  SPI_FLASH_MOSI;
inout  SPI_FLASH_MISO;
output  SPI_FLASH_HOLDn_net_vcc;
input  RESET;
output [3:0] LEDs_4Bits_TRI_O;
input [3:0] DIP_Switches_4Bits_TRI_I;
input  CLK_66MHZ;
inout  CDCE913_SDA;
inout  CDCE913_SCL;
input  axi_uartlite_0_RX_pin;
output  axi_uartlite_0_TX_pin;
output  axi_spi_0_SCK_O_pin;
output [0:0] axi_spi_0_SS_O_pin;
output  axi_spi_0_MOSI_O_pin;
input  axi_spi_0_MISO_I_pin;
input [0:7] axi_gpio_0_GPIO_IO_I_pin;
output [0:7] axi_gpio_0_GPIO_IO_O_pin;
output [0:7] axi_gpio_0_GPIO_IO_T_pin;
input  axi_iic_0_Sda_I_pin;
output  axi_iic_0_Sda_O_pin;
output  axi_iic_0_Sda_T_pin;
input  axi_iic_0_Scl_I_pin;
output  axi_iic_0_Scl_O_pin;
output  axi_iic_0_Scl_T_pin;
input [0:7] axi_gpio_2_GPIO_IO_I_pin;
output [0:7] axi_gpio_2_GPIO_IO_O_pin;
output [0:7] axi_gpio_2_GPIO_IO_T_pin;
inout [0:7] axi_gpio_1_GPIO_IO;

endmodule
