Sonoma (MAXREFDES14#) Code Documentation V01.00 Isolated EMP (Energy Measurement Processor)

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maximDeviceSpecificUtilities.c
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1
31 /*
32 * Copyright (C) 2012 Maxim Integrated Products, Inc., All Rights Reserved.
33 *
34 * Permission is hereby granted, free of charge, to any person obtaining a
35 * copy of this software and associated documentation files (the "Software"),
36 * to deal in the Software without restriction, including without limitation
37 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
38 * and/or sell copies of the Software, and to permit persons to whom the
39 * Software is furnished to do so, subject to the following conditions:
40 *
41 * The above copyright notice and this permission notice shall be included
42 * in all copies or substantial portions of the Software.
43 *
44 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS
45 * OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF
46 * MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.
47 * IN NO EVENT SHALL MAXIM INTEGRATED PRODUCTS BE LIABLE FOR ANY CLAIM, DAMAGES
48 * OR OTHER LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE,
49 * ARISING FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
50 * OTHER DEALINGS IN THE SOFTWARE.
51 *
52 * Except as contained in this notice, the name of Maxim Integrated Products
53 * shall not be used except as stated in the Maxim Integrated Products
54 * Branding Policy.
55 *
56 * The mere transfer of this software does not imply any licenses
57 * of trade secrets, proprietary technology, copyrights, patents,
58 * trademarks, maskwork rights, or any other form of intellectual
59 * property whatsoever. Maxim Integrated Products retains all ownership rights.
60 *
61 ***************************************************************************/
62
63 #include "xbasic_types.h"
64 #include "stdio.h"
65 #include "maximDeviceSpecificUtilities.h"
66 #include "utilities.h"
67
68
69 u32 read_reg(u8 uchRegAddr)
79 {
80 u8 uchRegValue[3];
81 u8 uchSPIWBuffer[2];
82
83 //preparing read command
84 uchSPIWBuffer[0] = uchRegAddr>>6;
85 uchSPIWBuffer[0] = (uchSPIWBuffer[0]<<2)+1;
86 uchSPIWBuffer[1] = 0x3F & uchRegAddr;
87 uchSPIWBuffer[1] = uchSPIWBuffer[1]<<2;
88
89 /* Write to the control register:
90 * MSB first
91 * Master transctions inhibit
92 * Slave select output follows data in slave select regitster
93 * Rx and Tx FIFO normal operation
94 * CPHA = CPOL = 1
95 * SPI master mode
96 * SPI system enabled
97 * Normal operation
98 */
99 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x60, 0x19E);
100
101 //CS high
102 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x70, 0xFFFFFFFF);
103
104 //CS low
105 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x70, 0xFFFFFFFE);
106
107 //Write 3 bytes to Tx FIFO
108 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x68, uchSPIWBuffer[0]);
109 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x68, uchSPIWBuffer[1]);
110 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x68, 0x00);
111 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x68, 0x00);
112 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x68, 0x00);
113
114 //Un-inhibit our SPI master to transfer the data
115 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x60, 0x09E);
116
117 //Wait for transaction to complete. Check to see if Tx_Empty flag is set before proceeding.
118 while( !(XSpi_ReadReg( XPAR_SPI_0_BASEADDR, 0x64 ) & 0x00000004) );
119
120 //CS high
121 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x70, 0xFFFFFFFF);
122
123 //Inhibit SPI master to prevent further action
124 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x60, 0x19E);
125
126 //Read a value from the Rx FIFO
127 uchRegValue[0]=XSpi_ReadReg(XPAR_SPI_0_BASEADDR, 0x6C);
128 //Read a value from the Rx FIFO
129 uchRegValue[0]=XSpi_ReadReg(XPAR_SPI_0_BASEADDR, 0x6C);
130 //Read a value from the Rx FIFO
131 uchRegValue[0]=XSpi_ReadReg(XPAR_SPI_0_BASEADDR, 0x6C);
132 //Read a value from the Rx FIFO
133 uchRegValue[1]=XSpi_ReadReg(XPAR_SPI_0_BASEADDR, 0x6C);
134 //Read a value from the Rx FIFO
135 uchRegValue[2]=XSpi_ReadReg(XPAR_SPI_0_BASEADDR, 0x6C);
136
137 return (uchRegValue[0]<<16) + (uchRegValue[1]<<8) + uchRegValue[2];
138
139 }
140
141 void write_reg(u8 uchRegAddr, u32 unRegValue)
152 {
153 u8 uchSPIWBuffer[5];
154 u8 uchDummy;
155
156 //preparing write command
157 uchSPIWBuffer[0] = uchRegAddr>>6;
158 uchSPIWBuffer[0] = (uchSPIWBuffer[0]<<2)+1;
159 uchSPIWBuffer[1] = 0x3F & uchRegAddr;
160 uchSPIWBuffer[1] = (uchSPIWBuffer[1]<<2)+2;
161 uchSPIWBuffer[2] = unRegValue>>16;
162 uchSPIWBuffer[3] = unRegValue>>8;
163 uchSPIWBuffer[4] = unRegValue;
164
165 /* Write to the control register:
166 * MSB first
167 * Master transctions inhibit
168 * Slave select output follows data in slave select regitster
169 * Rx and Tx FIFO normal operation
170 * CPHA = CPOL = 1
171 * SPI master mode
172 * SPI system enabled
173 * Normal operation
174 */
175 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x60, 0x19E);
176
177 //CS high
178 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x70, 0xFFFFFFFF);
179
180 //CS low
181 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x70, 0xFFFFFFFE);
182
183 //Write 3 bytes to Tx FIFO
184 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x68, uchSPIWBuffer[0]);
185 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x68, uchSPIWBuffer[1]);
186 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x68, uchSPIWBuffer[2]);
187 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x68, uchSPIWBuffer[3]);
188 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x68, uchSPIWBuffer[4]);
189
190 //Un-inhibit our SPI master to transfer the data
191 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x60, 0x09E);
192
193 //Wait for transaction to complete. Check to see if Tx_Empty flag is set before proceeding.
194 while( !(XSpi_ReadReg( XPAR_SPI_0_BASEADDR, 0x64 ) & 0x00000004) );
195
196 //CS high
197 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x70, 0xFFFFFFFF);
198
199 //Inhibit SPI master to prevent further action
200 XSpi_WriteReg(XPAR_SPI_0_BASEADDR, 0x60, 0x19E);
201
202 //Read a value from the Rx FIFO
203 uchDummy=XSpi_ReadReg(XPAR_SPI_0_BASEADDR, 0x6C);
204 //Read a value from the Rx FIFO
205 uchDummy=XSpi_ReadReg(XPAR_SPI_0_BASEADDR, 0x6C);
206 //Read a value from the Rx FIFO
207 uchDummy=XSpi_ReadReg(XPAR_SPI_0_BASEADDR, 0x6C);
208 //Read a value from the Rx FIFO
209 uchDummy=XSpi_ReadReg(XPAR_SPI_0_BASEADDR, 0x6C);
210 //Read a value from the Rx FIFO
211 uchDummy=XSpi_ReadReg(XPAR_SPI_0_BASEADDR, 0x6C);
212
213 }