`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date:    09:02:52 07/16/2012 
// Design Name: 
// Module Name:    top 
// Project Name: 
// Target Devices: 
// Tool versions: 
// Description: 
//
// Dependencies: 
//
// Revision: 
// Revision 0.01 - File Created
// Additional Comments: 
//
//////////////////////////////////////////////////////////////////////////////////
module topLevel(
	input wire CLOCK_Y2,
   //input wire CLOCK_Y3,
	input wire GPIO_DIP1,
	input wire GPIO_DIP2,
	input wire GPIO_DIP3,
	input wire GPIO_DIP4,
	
	output wire GPIO_LED1,
	output wire GPIO_LED2,
	output wire GPIO_LED3,
	output wire GPIO_LED4,
	
	input wire USER_RESET,
	
	input wire USB_RS232_RXD,
	output wire USB_RS232_TXD,
	
	inout wire SCL,
	inout wire SDA,
	
// DDR Address
	output wire [12:0] mcbx_dram_addr,
	output wire [1:0] mcbx_dram_ba,

// DDR Data	
	inout wire [15:0] mcbx_dram_dq,
	
// DDR Control
output wire rzq,
output wire mcbx_dram_cas_n,
output wire mcbx_dram_clk,
output wire mcbx_dram_clk_n,
output wire mcbx_dram_cke,
output wire mcbx_dram_ldm,
output wire mcbx_dram_dqs,
output wire mcbx_dram_ras_n,
output wire mcbx_dram_udm,
output wire mcbx_dram_udqs,
output wire mcbx_dram_we_n,


// SPI FLASH 	
	output wire SPI_SCK,
	output wire SPI_CS_n,
	inout wire SPI_MOSI_MISO0,
	inout wire SPI_MISO_MISO1,
	inout wire SPI_Wn_MISO2,
	inout wire SPI_HOLDn_MISO3,
	
// PMOD ports
inout wire [7:0]JA,  // J5
inout wire [7:0]JB	// J4
    );
	  
// These wires are used to connect the microblaze peripherals to the PMOD port muxes	  
wire uart0Tx;
wire uart0Rx;
wire [7:0] GPIO0_input;	
wire [7:0] GPIO0_output;	
wire [7:0] GPIO0_tristate;	
wire I2C_0_SDA_input;
wire I2C_0_SDA_output;
wire I2C_0_SDA_tristate;
wire I2C_0_SCL_input;
wire I2C_0_SCL_output;
wire I2C_0_SCL_tristate;
wire SPI_0_SS;
wire SPI_0_MOSI;
wire SPI_0_MISO;
wire SPI_0_SCLK;

// Port B wires (J4)
wire [7:0] GPIO1_IO;	

// Wires for the PMOD Mux selector
wire [7:0] GPIO2_input;	
wire [7:0] GPIO2_output;	
wire [7:0] GPIO2_tristate;	


// Instantiate the module
system cpu1 (
    .rzq(rzq), 
    .mcbx_dram_we_n(mcbx_dram_we_n), 
    .mcbx_dram_udqs(mcbx_dram_udqs), 
    .mcbx_dram_udm(mcbx_dram_udm), 
    .mcbx_dram_ras_n(mcbx_dram_ras_n), 
    .mcbx_dram_ldm(mcbx_dram_ldm), 
    .mcbx_dram_dqs(mcbx_dram_dqs), 
    .mcbx_dram_dq(mcbx_dram_dq[15:0]), 
    .mcbx_dram_clk_n(mcbx_dram_clk_n), 
    .mcbx_dram_clk(mcbx_dram_clk), 
    .mcbx_dram_cke(mcbx_dram_cke), 
    .mcbx_dram_cas_n(mcbx_dram_cas_n), 
    .mcbx_dram_ba(mcbx_dram_ba[1:0]), 
    .mcbx_dram_addr(mcbx_dram_addr[12:0]), 
    .USB_Uart_sout(USB_RS232_TXD), 
    .USB_Uart_sin(USB_RS232_RXD), 
    .SPI_FLASH_Wn_net_vcc(SPI_Wn_MISO2), 
    .SPI_FLASH_SS(SPI_CS_n), 
    .SPI_FLASH_SCLK(SPI_SCK), 
    .SPI_FLASH_MOSI(SPI_MOSI_MISO0), 
    .SPI_FLASH_MISO(SPI_MISO_MISO1), 
    .SPI_FLASH_HOLDn_net_vcc(SPI_HOLDn_MISO3), 
    .RESET(USER_RESET), 
    .LEDs_4Bits_TRI_O({GPIO_LED4,GPIO_LED3,GPIO_LED2,GPIO_LED1}), 
    .DIP_Switches_4Bits_TRI_I({GPIO_DIP4,GPIO_DIP3,GPIO_DIP2,GPIO_DIP1}), 
    .CLK_66MHZ(CLOCK_Y2), 
    .CDCE913_SDA(SDA), 
    .CDCE913_SCL(SCL),
	 // PMOD peripherals are below
    .axi_uartlite_0_RX_pin(uart0Rx), 
    .axi_uartlite_0_TX_pin(uart0Tx), 
    .axi_spi_0_SCK_O_pin(SPI_0_SCLK), 
    .axi_spi_0_SS_O_pin(SPI_0_SS), 
    .axi_spi_0_MOSI_O_pin(SPI_0_MOSI), 
    .axi_spi_0_MISO_I_pin(SPI_0_MISO), 
    .axi_gpio_0_GPIO_IO_I_pin(GPIO0_input[7:0]), 
    .axi_gpio_0_GPIO_IO_O_pin(GPIO0_output[7:0]), 
    .axi_gpio_0_GPIO_IO_T_pin(GPIO0_tristate[7:0]), 
    .axi_iic_0_Sda_I_pin(I2C_0_SDA_input), 
    .axi_iic_0_Sda_O_pin(I2C_0_SDA_output), 
    .axi_iic_0_Sda_T_pin(I2C_0_SDA_tristate), 
    .axi_iic_0_Scl_I_pin(I2C_0_SCL_input), 
    .axi_iic_0_Scl_O_pin(I2C_0_SCL_output), 
    .axi_iic_0_Scl_T_pin(I2C_0_SCL_tristate),
	 .axi_gpio_1_GPIO_IO(GPIO1_IO[7:0]),
	 .axi_gpio_2_GPIO_IO_I_pin(GPIO2_input[7:0]), 
    .axi_gpio_2_GPIO_IO_O_pin(GPIO2_output[7:0]), 
    .axi_gpio_2_GPIO_IO_T_pin(GPIO2_tristate[7:0])
    );

pModPortMuxWithI2C pmodPortAMux(
    .A(GPIO2_output[1:0]),
    .uartTx(uart0Tx),
    .uartRx(uart0Rx),
    .SPI_SS(SPI_0_SS),
    .SPI_MOSI(SPI_0_MOSI),
    .SPI_MISO(SPI_0_MISO),
    .SPI_SCK(SPI_0_SCLK),
	 .GPIO_outputFromMicroBlaze(GPIO0_output[3:0]),
	 .GPIO_inputToMicroBlaze(GPIO0_input[3:0]),
    .GPIO_tristate(GPIO0_tristate[3:0]),
	 .I2C_SDA_inputToMicroBlaze(I2C_0_SDA_input),
	 .I2C_SDA_outputFromMicroBlaze(I2C_0_SDA_output),
	 .I2C_SDA_tristate(I2C_0_SDA_tristate),
	 .I2C_SCL_inputToMicroBlaze(I2C_0_SCL_input),
	 .I2C_SCL_outputFromMicroBlaze(I2C_0_SCL_output),
	 .I2C_SCL_tristate(I2C_0_SCL_tristate),
    .pmodConnector(JA[3:0])
    );

	// The LX9 device does not have enough resources to add a full suite of peripherals
	// to the 2nd PMOD port.  Therefore, it is setup to (only) be an 8 bit GPIO interface
	assign JB[7:0] = GPIO1_IO[7:0];
 

	 // This code assigns the PMOD pins 7:4 to the GPIO for that port
	 assign GPIO0_input[7] = JA[7];
	 assign JA[7] = (GPIO0_tristate[7]==1) ? 1'bz : GPIO0_output[7];
	 assign GPIO0_input[6] = JA[6];
	 assign JA[6] = (GPIO0_tristate[6]==1) ? 1'bz : GPIO0_output[6];
	 assign GPIO0_input[5] = JA[5];
	 assign JA[5] = (GPIO0_tristate[5]==1) ? 1'bz : GPIO0_output[5];
	 assign GPIO0_input[4] = JA[4];
	 assign JA[4] = (GPIO0_tristate[4]==1) ? 1'bz : GPIO0_output[4];

	 
endmodule
