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// The following must be inserted into your Verilog file for this
// core to be instantiated. Change the instance name and port connections
// (in parentheses) to your own signal names.

//----------- Begin Cut here for INSTANTIATION Template ---// INST_TAG

  (* BOX_TYPE = "user_black_box" *)
  arm_system
    arm_system_i (
      .processing_system7_0_MIO ( processing_system7_0_MIO ),     // inout [53:0] processing_system7_0_MIO;
      .processing_system7_0_PS_SRSTB ( processing_system7_0_PS_SRSTB ),     // input processing_system7_0_PS_SRSTB;
      .processing_system7_0_PS_CLK ( processing_system7_0_PS_CLK ),     // input processing_system7_0_PS_CLK;
      .processing_system7_0_PS_PORB ( processing_system7_0_PS_PORB ),     // input processing_system7_0_PS_PORB;
      .processing_system7_0_DDR_Clk ( processing_system7_0_DDR_Clk ),     // inout processing_system7_0_DDR_Clk;
      .processing_system7_0_DDR_Clk_n ( processing_system7_0_DDR_Clk_n ),     // inout processing_system7_0_DDR_Clk_n;
      .processing_system7_0_DDR_CKE ( processing_system7_0_DDR_CKE ),     // inout processing_system7_0_DDR_CKE;
      .processing_system7_0_DDR_CS_n ( processing_system7_0_DDR_CS_n ),     // inout processing_system7_0_DDR_CS_n;
      .processing_system7_0_DDR_RAS_n ( processing_system7_0_DDR_RAS_n ),     // inout processing_system7_0_DDR_RAS_n;
      .processing_system7_0_DDR_CAS_n ( processing_system7_0_DDR_CAS_n ),     // inout processing_system7_0_DDR_CAS_n;
      .processing_system7_0_DDR_WEB_pin ( processing_system7_0_DDR_WEB_pin ),     // output processing_system7_0_DDR_WEB_pin;
      .processing_system7_0_DDR_BankAddr ( processing_system7_0_DDR_BankAddr ),     // inout [2:0] processing_system7_0_DDR_BankAddr;
      .processing_system7_0_DDR_Addr ( processing_system7_0_DDR_Addr ),     // inout [14:0] processing_system7_0_DDR_Addr;
      .processing_system7_0_DDR_ODT ( processing_system7_0_DDR_ODT ),     // inout processing_system7_0_DDR_ODT;
      .processing_system7_0_DDR_DRSTB ( processing_system7_0_DDR_DRSTB ),     // inout processing_system7_0_DDR_DRSTB;
      .processing_system7_0_DDR_DQ ( processing_system7_0_DDR_DQ ),     // inout [31:0] processing_system7_0_DDR_DQ;
      .processing_system7_0_DDR_DM ( processing_system7_0_DDR_DM ),     // inout [3:0] processing_system7_0_DDR_DM;
      .processing_system7_0_DDR_DQS ( processing_system7_0_DDR_DQS ),     // inout [3:0] processing_system7_0_DDR_DQS;
      .processing_system7_0_DDR_DQS_n ( processing_system7_0_DDR_DQS_n ),     // inout [3:0] processing_system7_0_DDR_DQS_n;
      .processing_system7_0_DDR_VRN ( processing_system7_0_DDR_VRN ),     // inout processing_system7_0_DDR_VRN;
      .processing_system7_0_DDR_VRP ( processing_system7_0_DDR_VRP ),     // inout processing_system7_0_DDR_VRP;
      .axi_gpio_OLED_GPIO_IO_O_pin ( axi_gpio_OLED_GPIO_IO_O_pin ),     // output [7:0] axi_gpio_OLED_GPIO_IO_O_pin;
      .axi_gpio_LED_GPIO_IO_pin ( axi_gpio_LED_GPIO_IO_pin ),     // inout [7:0] axi_gpio_LED_GPIO_IO_pin;
      .processing_system7_0_SPI1_SS1_O_pin ( processing_system7_0_SPI1_SS1_O_pin ),     // output processing_system7_0_SPI1_SS1_O_pin;
      .processing_system7_0_SPI1_SS2_O_pin ( processing_system7_0_SPI1_SS2_O_pin ),     // output processing_system7_0_SPI1_SS2_O_pin;
      .processing_system7_0_SPI1_SCLK_pin ( processing_system7_0_SPI1_SCLK_pin ),     // inout processing_system7_0_SPI1_SCLK_pin;
      .processing_system7_0_SPI1_MOSI_pin ( processing_system7_0_SPI1_MOSI_pin ),     // inout processing_system7_0_SPI1_MOSI_pin;
      .processing_system7_0_SPI1_MISO_pin ( processing_system7_0_SPI1_MISO_pin ),     // inout processing_system7_0_SPI1_MISO_pin;
      .processing_system7_0_SPI1_SS_pin ( processing_system7_0_SPI1_SS_pin )     // inout processing_system7_0_SPI1_SS_pin;
    );

// INST_TAG_END ------ End INSTANTIATION Template ---------

