/*****************************************************************************
 * MODIFICATION HISTORY:
 *
 * Ver   Who  Date     Changes
 * ----- ---- -------- ---------------------------------------------------
 * 3.02a sdm  05/30/11 Added Xuint64 typedef and XUINT64_MSW/XUINT64_LSW macros
 * 3.02a sdm  06/27/11 Added INST_SYNC and DATA_SYNC macros for all the CPUs
 * 3.02a sdm  07/07/11 Updated ppc440 boot.S to set guarded bit for all but
 *                     cacheable regions
 *                     Update ppc440/xil_cache.c to use CACHEABLE_REGION_MASK
 *                     generated by the cpu driver, for enabling caches
 * 3.02a sdm  07/08/11 Updated microblaze cache flush APIs based on write-back/
 *                     write-thru caches
 * 3.03a sdm  11/08/11 Updated microblaze xil_cache.h file to include 
 *		       xparameters.h file for CR630532 -  Xil_DCacheFlush()/
 *		       Xil_DCacheFlushRange() functions in standalone BSP v3_02a
 *                     for MicroBlaze will invalidate data in the cache instead 
 *		       of flushing it for writeback caches., 
 *****************************************************************************/
