Waived DRC Error Report
C:/svn_work/cc13xx/CC13xx_EM_Design/7x7/CC13xxEM-7XD-7793_4L/Cadence/allegro/CC13xxEM-7XD-7793_4L.brd
Mon Jun 22 15:16:25 2015

DRC Error Count Summary
DRC Error Type,DRC Error Count
Package to Package,1
Etch to Pad,1
Total DRC Errors,2

Detailed DRC Errors
Constraint Name,DRC Marker Location,Required Value,Actual Value,Constraint Source,Constraint Source Type,Element 1,Element 2,Comment
Package to Package Spacing,(130.950 120.600),0 MM,0.4 MM,NONE,DESIGN,"Shape "R11, Package Geometry/Place_Bound_Top"","Shape "R12, Package Geometry/Place_Bound_Top"",Antenna-SMA selctor
Shape to SMD Pin Spacing,(125.430 127.195),0.15 MM,0 MM,DEFAULT,NET SPACING CONSTRAINTS,"Shape "Dummy Net, Etch/Top"",Pin "A1.1 (N485535)",Antenna

