LTC3350 Register Map Tables

Resigter Map Formats:
Register Map
Condensed Table
Expanded Table



Register Map

SUB ADDR Name Bit[15] Bit[14] Bit[13] Bit[12] Bit[11] Bit[10] Bit[9] Bit[8] Bit[7] Bit[6] Bit[5] Bit[4] Bit[3] Bit[2] Bit[1] Bit[0]
0x00clr_alarms (R/W) clr_cap_lo clr_esr_hi clr_dtemp_hot clr_dtemp_cold clr_ichg_uc clr_iin_oc clr_vout_ov clr_vout_uv clr_vcap_ov clr_vcap_uv clr_vin_ov clr_vin_uv clr_gpi_ov clr_gpi_uv clr_cap_ov clr_cap_uv
0x01msk_alarms (R/W) msk_cap_lo msk_esr_hi msk_dtemp_hot msk_dtemp_cold msk_ichg_uc msk_iin_oc msk_vout_ov msk_vout_uv msk_vcap_ov msk_vcap_uv msk_vin_ov msk_vin_uv msk_gpi_ov msk_gpi_uv msk_cap_ov msk_cap_uv
0x02msk_mon_status (R/W) msk_mon_power_returned msk_mon_power_failed msk_mon_esr_failed msk_mon_cap_failed msk_mon_esr_done msk_mon_cap_done msk_mon_capesr_pending msk_mon_capesr_scheduled msk_mon_capesr_active
0x04cap_esr_per_CMD (R/W) cap_esr_per
0x05vcapfb_dac_CMD (R/W) vcapfb_dac
0x06vshunt_CMD (R/W) vshunt
0x07cap_uv_lvl_CMD (R/W) cap_uv_lvl
0x08cap_ov_lvl_CMD (R/W) cap_ov_lvl
0x09gpi_uv_lvl_CMD (R/W) gpi_uv_lvl
0x0Agpi_ov_lvl_CMD (R/W) gpi_ov_lvl
0x0Bvin_uv_lvl_CMD (R/W) vin_uv_lvl
0x0Cvin_ov_lvl_CMD (R/W) vin_ov_lvl
0x0Dvcap_uv_lvl_CMD (R/W) vcap_uv_lvl
0x0Evcap_ov_lvl_CMD (R/W) vcap_ov_lvl
0x0Fvout_uv_lvl_CMD (R/W) vout_uv_lvl
0x10vout_ov_lvl_CMD (R/W) vout_ov_lvl
0x11iin_oc_lvl_CMD (R/W) iin_oc_lvl
0x12ichg_uc_lvl_CMD (R/W) ichg_uc_lvl
0x13dtemp_cold_lvl_CMD (R/W) dtemp_cold_lvl
0x14dtemp_hot_lvl_CMD (R/W) dtemp_hot_lvl
0x15esr_hi_lvl_CMD (R/W) esr_hi_lvl
0x16cap_lo_lvl_CMD (R/W) cap_lo_lvl
0x17ctl_reg (R/W) ctl_cap_scale ctl_stop_capesr ctl_gpi_buffer_en ctl_strt_capesr
0x1Anum_caps_CMD (R) num_caps
0x1Bchrg_status (R) chrg_pfo chrg_ci chrg_dis chrg_bal chrg_shnt chrg_cappg chrg_input_ilim chrg_uvlo chrg_cv chrg_stepup chrg_stepdown
0x1Cmon_status (R) mon_power_returned mon_power_failed mon_esr_failed mon_cap_failed mon_esr_done mon_cap_done mon_capesr_pending mon_capesr_scheduled mon_capesr_active
0x1Dalarm_reg (R) alarm_cap_lo alarm_esr_hi alarm_dtemp_hot alarm_dtemp_cold alarm_ichg_uc alarm_iin_oc alarm_vout_ov alarm_vout_uv alarm_vcap_ov alarm_vcap_uv alarm_vin_ov alarm_vin_uv alarm_gpi_ov alarm_gpi_uv alarm_cap_ov alarm_cap_uv
0x1Emeas_cap_CMD (R) meas_cap
0x1Fmeas_esr_CMD (R) meas_esr
0x20meas_vcap1_CMD (R) meas_vcap1
0x21meas_vcap2_CMD (R) meas_vcap2
0x22meas_vcap3_CMD (R) meas_vcap3
0x23meas_vcap4_CMD (R) meas_vcap4
0x24meas_gpi_CMD (R) meas_gpi
0x25meas_vin_CMD (R) meas_vin
0x26meas_vcap_CMD (R) meas_vcap
0x27meas_vout_CMD (R) meas_vout
0x28meas_iin_CMD (R) meas_iin
0x29meas_ichg_CMD (R) meas_ichg
0x2Ameas_dtemp_CMD (R) meas_dtemp

Condensed Table

SYMBOL
SUB
ADDR
R/W
BITS
DEFAULT
DESCRIPTION
clr_alarms
0x00
R/W
15:0
0
Clear Alarms Register: This register is used to clear alarms caused by exceeding a programmed limit. Writing a one to any bit in this register will cause its respective alarm to be cleared. The one written to this register is automatically cleared when its respective alarm is cleared.
   clr_cap_lo
15
0
Clear capacitance low alarm
   clr_esr_hi
14
0
Clear ESR high alarm
   clr_dtemp_hot
13
0
Clear die temperature hot alarm
   clr_dtemp_cold
12
0
Clear die temperature cold alarm
   clr_ichg_uc
11
0
Clear charge undercurrent alarm
   clr_iin_oc
10
0
Clear input overcurrent alarm
   clr_vout_ov
9
0
Clear VOUT overvoltage alarm
   clr_vout_uv
8
0
Clear VOUT undervoltage alarm
   clr_vcap_ov
7
0
Clear VCAP overvoltage alarm
   clr_vcap_uv
6
0
Clear VCAP undervoltage alarm
   clr_vin_ov
5
0
Clear VIN overvoltage alarm
   clr_vin_uv
4
0
Clear VIN undervoltage alarm
   clr_gpi_ov
3
0
Clear GPI overvoltage alarm
   clr_gpi_uv
2
0
Clear GPI undervoltage alarm
   clr_cap_ov
1
0
Clear capacitor overvoltage alarm
   clr_cap_uv
0
0
Clear capacitor undervoltage alarm
msk_alarms
0x01
R/W
15:0
0
Mask Alarms Register: Writing a one to any bit in the Mask Alarms Register enables its respective alarm to trigger an SMBALERT.
   msk_cap_uv
0
0
Enable capacitor undervoltage alarm
   msk_cap_ov
1
0
Enable capacitor over voltage alarm
   msk_gpi_uv
2
0
Enable GPI undervoltage alarm
   msk_gpi_ov
3
0
Enable GPI overvoltage alarm
   msk_vin_uv
4
0
Enable VIN undervoltage alarm
   msk_vin_ov
5
0
Enable VIN overvoltage alarm
   msk_vcap_uv
6
0
Enable VCAP undervoltage alarm
   msk_vcap_ov
7
0
Enable VCAP overvoltage alarm
   msk_vout_uv
8
0
Enable VOUT undervoltage alarm
   msk_vout_ov
9
0
Enable VOUT overvoltage alarm
   msk_iin_oc
10
0
Enable input overcurrent alarm
   msk_ichg_uc
11
0
Enable charge undercurrent alarm
   msk_dtemp_cold
12
0
Enable die temperature cold alarm
   msk_dtemp_hot
13
0
Enable die temperature hot alarm
   msk_esr_hi
14
0
Enable ESR high alarm
   msk_cap_lo
15
0
Enable capacitance low alarm
msk_mon_status
0x02
R/W
9:0
0
Mask Monitor Status Register: Writing a one to any bit in this register enables a rising edge of its respective bit in the mon_status register to trigger an SMBALERT.
   msk_mon_capesr_active
0
0
Set the SMBALERT when there is a rising edge on mon_capesr_active
   msk_mon_capesr_scheduled
1
0
Set the SMBALERT when there is a rising edge on mon_capesr_scheduled
   msk_mon_capesr_pending
2
0
Set the SMBALERT when there is a rising edge on mon_capesr_pending
   msk_mon_cap_done
3
0
Set the SMBALERT when there is a rising edge on mon_cap_done
   msk_mon_esr_done
4
0
Set the SMBALERT when there is a rising edge on mon_esr_done
   msk_mon_cap_failed
5
0
Set the SMBALERT when there is a rising edge on mon_cap_failed
   msk_mon_esr_failed
6
0
Set the SMBALERT when there is a rising edge on mon_esr_failed
   msk_mon_power_failed
8
0
Set the SMBALERT when there is a rising edge on mon_power_failed
   msk_mon_power_returned
9
0
Set the SMBALERT when there is a rising edge on mon_power_returned
cap_esr_per
0x04
R/W
15:0
0
Capacitance and ESR Measurement Period: This register sets the period of repeated capacitance and ESR measurements. Each LSB represents 10 seconds. Capacitance and ESR measurements will not repeat if this register is zero.
vcapfb_dac
0x05
R/W
3:0
15
VCAP Regulation Reference: This register is used to program the capacitor voltage feedback loop's reference voltage. Only bits 3:0 are active. CAPFBREF = 37.5mV * vcapfb_dac + 637.5mV
vshunt
0x06
R/W
15:0
14745
Shunt Voltage Register: This register programs the shunt voltage for each capacitor in the stack. The charger will limit current and the active shunts will shunt current to prevent this voltage from being exceeded. As a capacitor voltage nears this level, the charge current will be reduced. This should be programmed higher than the intended final balanced individual capacitor voltage. Setting this register to 0x0000 disables the shunt. 183.5uV per LSB.
cap_uv_lvl
0x07
R/W
15:0
0
Capacitor Undervoltage Level: This is an alarm threshold for each individual capacitor voltage in the stack. If enabled, any capacitor voltage falling below this level will trigger an alarm and an SMBALERT. 183.5uV per LSB.
cap_ov_lvl
0x08
R/W
15:0
0
Capacitor Overvoltage Level: This is an alarm threshold for each individual capacitor in the stack. If enabled, any capacitor voltage rising above this level will trigger an alarm and an SMBALERT. 183.5uV per LSB
gpi_uv_lvl
0x09
R/W
15:0
0
General Purpose Input Undervoltage Level: This is an alarm threshold for the GPI pin. If enabled, the voltage falling below this level will trigger an alarm and an SMBALERT. 183.5uV per LSB
gpi_ov_lvl
0x0A
R/W
15:0
0
General Purpose Input Overvoltage Level: This is an alarm threshold for the GPI pin. If enabled, the voltage rising above this level will trigger an alarm and an SMBALERT. 183.5uV per LSB
vin_uv_lvl
0x0B
R/W
15:0
0
VIN Undervoltage Level: This is an alarm threshold for the input voltage. If enabled, the voltage falling below this level will trigger an alarm and an SMBALERT. 2.21mV per LSB
vin_ov_lvl
0x0C
R/W
15:0
0
VIN Overvoltage Level: This is an alarm threshold for the input voltage. If enabled, the voltage rising above this level will trigger an alarm and an SMBALERT. 2.21mV per LSB
vcap_uv_lvl
0x0D
R/W
15:0
0
VCAP Undervoltage Level: This is an alarm threshold for the capacitor stack voltage. If enabled, the voltage falling below this level will trigger an alarm and an SMBALERT. 1.476mV per LSB
vcap_ov_lvl
0x0E
R/W
15:0
0
VCAP Overvoltage Level: This is an alarm threshold for the capacitor stack voltage. If enabled, the voltage rising above this level will trigger an alarm and an SMBALERT. 1.476mV per LSB
vout_uv_lvl
0x0F
R/W
15:0
0
VOUT Undervoltage Level: This is an alarm threshold for the output voltage. If enabled, the voltage falling below this level will trigger an alarm and an SMBALERT. 2.21mV per LSB
vout_ov_lvl
0x10
R/W
15:0
0
VOUT Overvoltage Level: This is an alarm threshold for the output voltage. If enabled, the voltage rising above this level will trigger an alarm and an SMBALERT. 2.21mV per LSB
iin_oc_lvl
0x11
R/W
15:0
0
Input Overcurrent Level: This is an alarm threshold for the input current. If enabled, the current rising above this level will trigger an alarm and an SMBALERT. 1.983uV/RSNSI per LSB
ichg_uc_lvl
0x12
R/W
15:0
0
Charge Undercurrent Level: This is an alarm threshold for the charge current. If enabled, the current falling below this level will trigger an alarm and an SMBALERT. 1.983uV/RSNSC per LSB
dtemp_cold_lvl
0x13
R/W
15:0
0
Die Temperature Cold Level: This is an alarm threshold for the die temperature. If enabled, the die temperature falling below this level will trigger an alarm and an SMBALERT. Temperature = 0.028C per LSB - 251.4C
dtemp_hot_lvl
0x14
R/W
15:0
0
Die Temperature Hot Level: This is an alarm threshold for the die temperature. If enabled, the die temperature rising above this level will trigger an alarm and an SMBALERT. Temperature = 0.028C per LSB - 251.4C
esr_hi_lvl
0x15
R/W
15:0
0
ESR High Level: This is an alarm threshold for the measured stack ESR. If enabled, a measurement of stack ESR exceeding this level will trigger an alarm and an SMBALERT. RSNSC/64 per LSB.
cap_lo_lvl
0x16
R/W
15:0
0
Capacitance Low Level: This is an alarm threshold for the measured stack capacitance. If enabled, if the measured stack capacitance is less than this level it will trigger an alarm and an SMBALERT. When ctl_cap_scale is set to 1, capacitance is 3.36uF * RT/RTST per LSB. When ctl_cap_scale is set to 0 it is 336uF * RT/RTST per LSB.
ctl_reg
0x17
R/W
3:0
0
Control Register: Several Control Functions are grouped into this register.
   ctl_strt_capesr
0
0
Begin a capacitance and ESR measurement when possible; this bit clears itself once a cycle begins.
   ctl_gpi_buffer_en
1
0
A one in this bit location enables the input buffer on the GPI pin. With a zero in this location the GPI pin is measured without the buffer.
   ctl_stop_capesr
2
0
Stops an active capacitance/ESR measurement.
   ctl_cap_scale
3
0
Increases capacitor measurement resolution by 100x, this is used when measuring smaller capacitors.
num_caps
0x1A
R
1:0
N/A
Number of Capacitors. This register shows the state of the CAP_SLCT1, CAP_SLCT0 pins. The value read in this register is the number of capacitors programmed minus one.
chrg_status
0x1B
R
11:0
N/A
Charger Status Register: This register provides real time status information about the state of the charger system. Each bit is active high.
   chrg_stepdown
0
N/A
The synchronous controller is in step-down mode (charging)
   chrg_stepup
1
N/A
The synchronous controller is in step-up mode (backup)
   chrg_cv
2
N/A
The charger is in constant voltage mode
   chrg_uvlo
3
N/A
The charger is in under voltage lockout
   chrg_input_ilim
4
N/A
The charger is in input current limit
   chrg_cappg
5
N/A
The capacitor voltage is above power good threshold
   chrg_shnt
6
N/A
The capacitor manager is shunting
   chrg_bal
7
N/A
The capacitor manager is balancing
   chrg_dis
8
N/A
The charger is temporarily disabled for capacitance measurement
   chrg_ci
9
N/A
The charger is in constant current mode
   chrg_pfo
11
N/A
Input voltage is below PFI threshold
mon_status
0x1C
R
9:0
N/A
Monitor Status: This register provides real time status information about the state of the monitoring system. Each bit is active high.
   mon_capesr_active
0
N/A
Capacitance/ESR measurement is in progress
   mon_capesr_scheduled
1
N/A
Waiting programmed time to begin a capacitance/ESR measurement
   mon_capesr_pending
2
N/A
Waiting for satisfactory conditions to begin a capacitance/ESR measurement
   mon_cap_done
3
N/A
Capacitance measurement has completed
   mon_esr_done
4
N/A
ESR Measurement has completed
   mon_cap_failed
5
N/A
The last attempted capacitance measurement was unable to complete
   mon_esr_failed
6
N/A
The last attempted ESR measurement was unable to complete
   mon_power_failed
8
N/A
This bit is set when VIN falls below the PFI threshold or the charger is unable to charge. It is cleared only when power returns and the charger is able to charge.
   mon_power_returned
9
N/A
This bit is set when the input is above the PFI threshold and the charger is able to charge. It is cleared only when mon_power_failed is set.
alarm_reg
0x1D
R
15:0
N/A
Alarms Register: A one in any bit in the register indicates its respective alarm has triggered. All bits are active high.
   alarm_cap_uv
0
N/A
Capacitor undervoltage alarm
   alarm_cap_ov
1
N/A
Capacitor overvoltage alarm
   alarm_gpi_uv
2
N/A
GPI undervoltage alarm
   alarm_gpi_ov
3
N/A
GPI overvoltage alarm
   alarm_vin_uv
4
N/A
VIN undervoltage alarm
   alarm_vin_ov
5
N/A
VIN overvoltage alarm
   alarm_vcap_uv
6
N/A
VCAP undervoltage alarm
   alarm_vcap_ov
7
N/A
VCAP overvoltage alarm
   alarm_vout_uv
8
N/A
VOUT undervoltage alarm
   alarm_vout_ov
9
N/A
VOUT overvoltage alarm
   alarm_iin_oc
10
N/A
Input overcurrent alarm
   alarm_ichg_uc
11
N/A
Charge undercurrent alarm
   alarm_dtemp_cold
12
N/A
Die temperature cold alarm
   alarm_dtemp_hot
13
N/A
Die temperature hot alarm
   alarm_esr_hi
14
N/A
ESR high alarm
   alarm_cap_lo
15
N/A
Capacitance low alarm
meas_cap
0x1E
R
15:0
N/A
Measured capacitor stack capacitance value. When ctl_cap_scale is set to 1, capacitance is 3.36uF * RT/RTST per LSB. When ctl_cap_scale is set to 0 it is 336uF * RT/RTST per LSB.
meas_esr
0x1F
R
15:0
N/A
Measured capacitor stack equivalent series resistance (ESR) value. RSNSC/64 per LSB
meas_vcap1
0x20
R
15:0
N/A
Measured voltage between the CAP1 and CAPRTN pins. 183.5uV per LSB
meas_vcap2
0x21
R
15:0
N/A
Measured voltage between the CAP2 and CAP1 pins. 183.5uV per LSB
meas_vcap3
0x22
R
15:0
N/A
Measured voltage between the CAP3 and CAP2 pins. 183.5uV per LSB
meas_vcap4
0x23
R
15:0
N/A
Measured voltage between the CAP4 and CAP3 pins. 183.5uV per LSB
meas_gpi
0x24
R
15:0
N/A
Measurement of GPI pin voltage. 183.5uV per LSB
meas_vin
0x25
R
15:0
N/A
Measured Input Voltage. 2.21mV per LSB
meas_vcap
0x26
R
15:0
N/A
Measured Capacitor Stack Voltage. 1.476mV per LSB.
meas_vout
0x27
R
15:0
N/A
Measured Output Voltage. 2.21mV per LSB.
meas_iin
0x28
R
15:0
N/A
Measured Input Current. 1.983uV/RSNSI per LSB
meas_ichg
0x29
R
15:0
N/A
Measured Charge Current. 1.983uV/RSNSC per LSB
meas_dtemp
0x2A
R
15:0
N/A
Measured die temperature. Temperature = 0.028C per LSB - 251.4C

Expanded Table

 
clr_alarms   Address: 0x00 (R/W)
Clear Alarms Register: This register is used to clear alarms caused by exceeding a programmed limit. Writing a one to any bit in this register will cause its respective alarm to be cleared. The one written to this register is automatically cleared when its respective alarm is cleared.
Bit 15: clr_cap_lo (Default = 0)
Clear capacitance low alarm
Bit 14: clr_esr_hi (Default = 0)
Clear ESR high alarm
Bit 13: clr_dtemp_hot (Default = 0)
Clear die temperature hot alarm
Bit 12: clr_dtemp_cold (Default = 0)
Clear die temperature cold alarm
Bit 11: clr_ichg_uc (Default = 0)
Clear charge undercurrent alarm
Bit 10: clr_iin_oc (Default = 0)
Clear input overcurrent alarm
Bit 9: clr_vout_ov (Default = 0)
Clear VOUT overvoltage alarm
Bit 8: clr_vout_uv (Default = 0)
Clear VOUT undervoltage alarm
Bit 7: clr_vcap_ov (Default = 0)
Clear VCAP overvoltage alarm
Bit 6: clr_vcap_uv (Default = 0)
Clear VCAP undervoltage alarm
Bit 5: clr_vin_ov (Default = 0)
Clear VIN overvoltage alarm
Bit 4: clr_vin_uv (Default = 0)
Clear VIN undervoltage alarm
Bit 3: clr_gpi_ov (Default = 0)
Clear GPI overvoltage alarm
Bit 2: clr_gpi_uv (Default = 0)
Clear GPI undervoltage alarm
Bit 1: clr_cap_ov (Default = 0)
Clear capacitor overvoltage alarm
Bit 0: clr_cap_uv (Default = 0)
Clear capacitor undervoltage alarm
 
msk_alarms   Address: 0x01 (R/W)
Mask Alarms Register: Writing a one to any bit in the Mask Alarms Register enables its respective alarm to trigger an SMBALERT.
Bit 0: msk_cap_uv (Default = 0)
Enable capacitor undervoltage alarm
Bit 1: msk_cap_ov (Default = 0)
Enable capacitor over voltage alarm
Bit 2: msk_gpi_uv (Default = 0)
Enable GPI undervoltage alarm
Bit 3: msk_gpi_ov (Default = 0)
Enable GPI overvoltage alarm
Bit 4: msk_vin_uv (Default = 0)
Enable VIN undervoltage alarm
Bit 5: msk_vin_ov (Default = 0)
Enable VIN overvoltage alarm
Bit 6: msk_vcap_uv (Default = 0)
Enable VCAP undervoltage alarm
Bit 7: msk_vcap_ov (Default = 0)
Enable VCAP overvoltage alarm
Bit 8: msk_vout_uv (Default = 0)
Enable VOUT undervoltage alarm
Bit 9: msk_vout_ov (Default = 0)
Enable VOUT overvoltage alarm
Bit 10: msk_iin_oc (Default = 0)
Enable input overcurrent alarm
Bit 11: msk_ichg_uc (Default = 0)
Enable charge undercurrent alarm
Bit 12: msk_dtemp_cold (Default = 0)
Enable die temperature cold alarm
Bit 13: msk_dtemp_hot (Default = 0)
Enable die temperature hot alarm
Bit 14: msk_esr_hi (Default = 0)
Enable ESR high alarm
Bit 15: msk_cap_lo (Default = 0)
Enable capacitance low alarm
 
msk_mon_status   Address: 0x02 (R/W)
Mask Monitor Status Register: Writing a one to any bit in this register enables a rising edge of its respective bit in the mon_status register to trigger an SMBALERT.
Bit 0: msk_mon_capesr_active (Default = 0)
Set the SMBALERT when there is a rising edge on mon_capesr_active
Bit 1: msk_mon_capesr_scheduled (Default = 0)
Set the SMBALERT when there is a rising edge on mon_capesr_scheduled
Bit 2: msk_mon_capesr_pending (Default = 0)
Set the SMBALERT when there is a rising edge on mon_capesr_pending
Bit 3: msk_mon_cap_done (Default = 0)
Set the SMBALERT when there is a rising edge on mon_cap_done
Bit 4: msk_mon_esr_done (Default = 0)
Set the SMBALERT when there is a rising edge on mon_esr_done
Bit 5: msk_mon_cap_failed (Default = 0)
Set the SMBALERT when there is a rising edge on mon_cap_failed
Bit 6: msk_mon_esr_failed (Default = 0)
Set the SMBALERT when there is a rising edge on mon_esr_failed
Bit 8: msk_mon_power_failed (Default = 0)
Set the SMBALERT when there is a rising edge on mon_power_failed
Bit 9: msk_mon_power_returned (Default = 0)
Set the SMBALERT when there is a rising edge on mon_power_returned
 
cap_esr_per_CMD   Address: 0x04 (R/W)
Bits [15:0]: cap_esr_per (Default = 0)
Capacitance and ESR Measurement Period: This register sets the period of repeated capacitance and ESR measurements. Each LSB represents 10 seconds. Capacitance and ESR measurements will not repeat if this register is zero.
 
vcapfb_dac_CMD   Address: 0x05 (R/W)
Bits [3:0]: vcapfb_dac (Default = 15)
VCAP Regulation Reference: This register is used to program the capacitor voltage feedback loop's reference voltage. Only bits 3:0 are active. CAPFBREF = 37.5mV * vcapfb_dac + 637.5mV
 
vshunt_CMD   Address: 0x06 (R/W)
Bits [15:0]: vshunt (Default = 14745)
Shunt Voltage Register: This register programs the shunt voltage for each capacitor in the stack. The charger will limit current and the active shunts will shunt current to prevent this voltage from being exceeded. As a capacitor voltage nears this level, the charge current will be reduced. This should be programmed higher than the intended final balanced individual capacitor voltage. Setting this register to 0x0000 disables the shunt. 183.5uV per LSB.
 
cap_uv_lvl_CMD   Address: 0x07 (R/W)
Bits [15:0]: cap_uv_lvl (Default = 0)
Capacitor Undervoltage Level: This is an alarm threshold for each individual capacitor voltage in the stack. If enabled, any capacitor voltage falling below this level will trigger an alarm and an SMBALERT. 183.5uV per LSB.
 
cap_ov_lvl_CMD   Address: 0x08 (R/W)
Bits [15:0]: cap_ov_lvl (Default = 0)
Capacitor Overvoltage Level: This is an alarm threshold for each individual capacitor in the stack. If enabled, any capacitor voltage rising above this level will trigger an alarm and an SMBALERT. 183.5uV per LSB
 
gpi_uv_lvl_CMD   Address: 0x09 (R/W)
Bits [15:0]: gpi_uv_lvl (Default = 0)
General Purpose Input Undervoltage Level: This is an alarm threshold for the GPI pin. If enabled, the voltage falling below this level will trigger an alarm and an SMBALERT. 183.5uV per LSB
 
gpi_ov_lvl_CMD   Address: 0x0A (R/W)
Bits [15:0]: gpi_ov_lvl (Default = 0)
General Purpose Input Overvoltage Level: This is an alarm threshold for the GPI pin. If enabled, the voltage rising above this level will trigger an alarm and an SMBALERT. 183.5uV per LSB
 
vin_uv_lvl_CMD   Address: 0x0B (R/W)
Bits [15:0]: vin_uv_lvl (Default = 0)
VIN Undervoltage Level: This is an alarm threshold for the input voltage. If enabled, the voltage falling below this level will trigger an alarm and an SMBALERT. 2.21mV per LSB
 
vin_ov_lvl_CMD   Address: 0x0C (R/W)
Bits [15:0]: vin_ov_lvl (Default = 0)
VIN Overvoltage Level: This is an alarm threshold for the input voltage. If enabled, the voltage rising above this level will trigger an alarm and an SMBALERT. 2.21mV per LSB
 
vcap_uv_lvl_CMD   Address: 0x0D (R/W)
Bits [15:0]: vcap_uv_lvl (Default = 0)
VCAP Undervoltage Level: This is an alarm threshold for the capacitor stack voltage. If enabled, the voltage falling below this level will trigger an alarm and an SMBALERT. 1.476mV per LSB
 
vcap_ov_lvl_CMD   Address: 0x0E (R/W)
Bits [15:0]: vcap_ov_lvl (Default = 0)
VCAP Overvoltage Level: This is an alarm threshold for the capacitor stack voltage. If enabled, the voltage rising above this level will trigger an alarm and an SMBALERT. 1.476mV per LSB
 
vout_uv_lvl_CMD   Address: 0x0F (R/W)
Bits [15:0]: vout_uv_lvl (Default = 0)
VOUT Undervoltage Level: This is an alarm threshold for the output voltage. If enabled, the voltage falling below this level will trigger an alarm and an SMBALERT. 2.21mV per LSB
 
vout_ov_lvl_CMD   Address: 0x10 (R/W)
Bits [15:0]: vout_ov_lvl (Default = 0)
VOUT Overvoltage Level: This is an alarm threshold for the output voltage. If enabled, the voltage rising above this level will trigger an alarm and an SMBALERT. 2.21mV per LSB
 
iin_oc_lvl_CMD   Address: 0x11 (R/W)
Bits [15:0]: iin_oc_lvl (Default = 0)
Input Overcurrent Level: This is an alarm threshold for the input current. If enabled, the current rising above this level will trigger an alarm and an SMBALERT. 1.983uV/RSNSI per LSB
 
ichg_uc_lvl_CMD   Address: 0x12 (R/W)
Bits [15:0]: ichg_uc_lvl (Default = 0)
Charge Undercurrent Level: This is an alarm threshold for the charge current. If enabled, the current falling below this level will trigger an alarm and an SMBALERT. 1.983uV/RSNSC per LSB
 
dtemp_cold_lvl_CMD   Address: 0x13 (R/W)
Bits [15:0]: dtemp_cold_lvl (Default = 0)
Die Temperature Cold Level: This is an alarm threshold for the die temperature. If enabled, the die temperature falling below this level will trigger an alarm and an SMBALERT. Temperature = 0.028C per LSB - 251.4C
 
dtemp_hot_lvl_CMD   Address: 0x14 (R/W)
Bits [15:0]: dtemp_hot_lvl (Default = 0)
Die Temperature Hot Level: This is an alarm threshold for the die temperature. If enabled, the die temperature rising above this level will trigger an alarm and an SMBALERT. Temperature = 0.028C per LSB - 251.4C
 
esr_hi_lvl_CMD   Address: 0x15 (R/W)
Bits [15:0]: esr_hi_lvl (Default = 0)
ESR High Level: This is an alarm threshold for the measured stack ESR. If enabled, a measurement of stack ESR exceeding this level will trigger an alarm and an SMBALERT. RSNSC/64 per LSB.
 
cap_lo_lvl_CMD   Address: 0x16 (R/W)
Bits [15:0]: cap_lo_lvl (Default = 0)
Capacitance Low Level: This is an alarm threshold for the measured stack capacitance. If enabled, if the measured stack capacitance is less than this level it will trigger an alarm and an SMBALERT. When ctl_cap_scale is set to 1, capacitance is 3.36uF * RT/RTST per LSB. When ctl_cap_scale is set to 0 it is 336uF * RT/RTST per LSB.
 
ctl_reg   Address: 0x17 (R/W)
Control Register: Several Control Functions are grouped into this register.
Bit 0: ctl_strt_capesr (Default = 0)
Begin a capacitance and ESR measurement when possible; this bit clears itself once a cycle begins.
1: start
Bit 1: ctl_gpi_buffer_en (Default = 0)
A one in this bit location enables the input buffer on the GPI pin. With a zero in this location the GPI pin is measured without the buffer.
Bit 2: ctl_stop_capesr (Default = 0)
Stops an active capacitance/ESR measurement.
1: stop
Bit 3: ctl_cap_scale (Default = 0)
Increases capacitor measurement resolution by 100x, this is used when measuring smaller capacitors.
1: small
0: large
 
num_caps_CMD   Address: 0x1A (R)
Bits [1:0]: num_caps
Number of Capacitors. This register shows the state of the CAP_SLCT1, CAP_SLCT0 pins. The value read in this register is the number of capacitors programmed minus one.
 
chrg_status   Address: 0x1B (R)
Charger Status Register: This register provides real time status information about the state of the charger system. Each bit is active high.
Bit 0: chrg_stepdown
The synchronous controller is in step-down mode (charging)
Bit 1: chrg_stepup
The synchronous controller is in step-up mode (backup)
Bit 2: chrg_cv
The charger is in constant voltage mode
Bit 3: chrg_uvlo
The charger is in under voltage lockout
Bit 4: chrg_input_ilim
The charger is in input current limit
Bit 5: chrg_cappg
The capacitor voltage is above power good threshold
Bit 6: chrg_shnt
The capacitor manager is shunting
Bit 7: chrg_bal
The capacitor manager is balancing
Bit 8: chrg_dis
The charger is temporarily disabled for capacitance measurement
Bit 9: chrg_ci
The charger is in constant current mode
Bit 11: chrg_pfo
Input voltage is below PFI threshold
 
mon_status   Address: 0x1C (R)
Monitor Status: This register provides real time status information about the state of the monitoring system. Each bit is active high.
Bit 0: mon_capesr_active
Capacitance/ESR measurement is in progress
Bit 1: mon_capesr_scheduled
Waiting programmed time to begin a capacitance/ESR measurement
Bit 2: mon_capesr_pending
Waiting for satisfactory conditions to begin a capacitance/ESR measurement
Bit 3: mon_cap_done
Capacitance measurement has completed
Bit 4: mon_esr_done
ESR Measurement has completed
Bit 5: mon_cap_failed
The last attempted capacitance measurement was unable to complete
Bit 6: mon_esr_failed
The last attempted ESR measurement was unable to complete
Bit 8: mon_power_failed
This bit is set when VIN falls below the PFI threshold or the charger is unable to charge. It is cleared only when power returns and the charger is able to charge.
Bit 9: mon_power_returned
This bit is set when the input is above the PFI threshold and the charger is able to charge. It is cleared only when mon_power_failed is set.
 
alarm_reg   Address: 0x1D (R)
Alarms Register: A one in any bit in the register indicates its respective alarm has triggered. All bits are active high.
Bit 0: alarm_cap_uv
Capacitor undervoltage alarm
Bit 1: alarm_cap_ov
Capacitor overvoltage alarm
Bit 2: alarm_gpi_uv
GPI undervoltage alarm
Bit 3: alarm_gpi_ov
GPI overvoltage alarm
Bit 4: alarm_vin_uv
VIN undervoltage alarm
Bit 5: alarm_vin_ov
VIN overvoltage alarm
Bit 6: alarm_vcap_uv
VCAP undervoltage alarm
Bit 7: alarm_vcap_ov
VCAP overvoltage alarm
Bit 8: alarm_vout_uv
VOUT undervoltage alarm
Bit 9: alarm_vout_ov
VOUT overvoltage alarm
Bit 10: alarm_iin_oc
Input overcurrent alarm
Bit 11: alarm_ichg_uc
Charge undercurrent alarm
Bit 12: alarm_dtemp_cold
Die temperature cold alarm
Bit 13: alarm_dtemp_hot
Die temperature hot alarm
Bit 14: alarm_esr_hi
ESR high alarm
Bit 15: alarm_cap_lo
Capacitance low alarm
 
meas_cap_CMD   Address: 0x1E (R)
Bits [15:0]: meas_cap
Measured capacitor stack capacitance value. When ctl_cap_scale is set to 1, capacitance is 3.36uF * RT/RTST per LSB. When ctl_cap_scale is set to 0 it is 336uF * RT/RTST per LSB.
 
meas_esr_CMD   Address: 0x1F (R)
Bits [15:0]: meas_esr
Measured capacitor stack equivalent series resistance (ESR) value. RSNSC/64 per LSB
 
meas_vcap1_CMD   Address: 0x20 (R)
Bits [15:0]: meas_vcap1
Measured voltage between the CAP1 and CAPRTN pins. 183.5uV per LSB
 
meas_vcap2_CMD   Address: 0x21 (R)
Bits [15:0]: meas_vcap2
Measured voltage between the CAP2 and CAP1 pins. 183.5uV per LSB
 
meas_vcap3_CMD   Address: 0x22 (R)
Bits [15:0]: meas_vcap3
Measured voltage between the CAP3 and CAP2 pins. 183.5uV per LSB
 
meas_vcap4_CMD   Address: 0x23 (R)
Bits [15:0]: meas_vcap4
Measured voltage between the CAP4 and CAP3 pins. 183.5uV per LSB
 
meas_gpi_CMD   Address: 0x24 (R)
Bits [15:0]: meas_gpi
Measurement of GPI pin voltage. 183.5uV per LSB
 
meas_vin_CMD   Address: 0x25 (R)
Bits [15:0]: meas_vin
Measured Input Voltage. 2.21mV per LSB
 
meas_vcap_CMD   Address: 0x26 (R)
Bits [15:0]: meas_vcap
Measured Capacitor Stack Voltage. 1.476mV per LSB.
 
meas_vout_CMD   Address: 0x27 (R)
Bits [15:0]: meas_vout
Measured Output Voltage. 2.21mV per LSB.
 
meas_iin_CMD   Address: 0x28 (R)
Bits [15:0]: meas_iin
Measured Input Current. 1.983uV/RSNSI per LSB
 
meas_ichg_CMD   Address: 0x29 (R)
Bits [15:0]: meas_ichg
Measured Charge Current. 1.983uV/RSNSC per LSB
 
meas_dtemp_CMD   Address: 0x2A (R)
Bits [15:0]: meas_dtemp
Measured die temperature. Temperature = 0.028C per LSB - 251.4C