| |
| clr_alarms Address: 0x00 (R/W) |
| Clear Alarms Register: This register is used to clear alarms caused by exceeding a programmed limit. Writing a one to any bit in this register will cause its respective alarm to be cleared. The one written to this register is automatically cleared when its respective alarm is cleared. |
|
Bit 15: |
clr_cap_lo (Default = 0) |
|
Clear capacitance low alarm |
|
Bit 14: |
clr_esr_hi (Default = 0) |
|
Clear ESR high alarm |
|
Bit 13: |
clr_dtemp_hot (Default = 0) |
|
Clear die temperature hot alarm |
|
Bit 12: |
clr_dtemp_cold (Default = 0) |
|
Clear die temperature cold alarm |
|
Bit 11: |
clr_ichg_uc (Default = 0) |
|
Clear charge undercurrent alarm |
|
Bit 10: |
clr_iin_oc (Default = 0) |
|
Clear input overcurrent alarm |
|
Bit 9: |
clr_vout_ov (Default = 0) |
|
Clear VOUT overvoltage alarm |
|
Bit 8: |
clr_vout_uv (Default = 0) |
|
Clear VOUT undervoltage alarm |
|
Bit 7: |
clr_vcap_ov (Default = 0) |
|
Clear VCAP overvoltage alarm |
|
Bit 6: |
clr_vcap_uv (Default = 0) |
|
Clear VCAP undervoltage alarm |
|
Bit 5: |
clr_vin_ov (Default = 0) |
|
Clear VIN overvoltage alarm |
|
Bit 4: |
clr_vin_uv (Default = 0) |
|
Clear VIN undervoltage alarm |
|
Bit 3: |
clr_gpi_ov (Default = 0) |
|
Clear GPI overvoltage alarm |
|
Bit 2: |
clr_gpi_uv (Default = 0) |
|
Clear GPI undervoltage alarm |
|
Bit 1: |
clr_cap_ov (Default = 0) |
|
Clear capacitor overvoltage alarm |
|
Bit 0: |
clr_cap_uv (Default = 0) |
|
Clear capacitor undervoltage alarm |
| |
| msk_alarms Address: 0x01 (R/W) |
| Mask Alarms Register: Writing a one to any bit in the Mask Alarms Register enables its respective alarm to trigger an SMBALERT. |
|
Bit 0: |
msk_cap_uv (Default = 0) |
|
Enable capacitor undervoltage alarm |
|
Bit 1: |
msk_cap_ov (Default = 0) |
|
Enable capacitor over voltage alarm |
|
Bit 2: |
msk_gpi_uv (Default = 0) |
|
Enable GPI undervoltage alarm |
|
Bit 3: |
msk_gpi_ov (Default = 0) |
|
Enable GPI overvoltage alarm |
|
Bit 4: |
msk_vin_uv (Default = 0) |
|
Enable VIN undervoltage alarm |
|
Bit 5: |
msk_vin_ov (Default = 0) |
|
Enable VIN overvoltage alarm |
|
Bit 6: |
msk_vcap_uv (Default = 0) |
|
Enable VCAP undervoltage alarm |
|
Bit 7: |
msk_vcap_ov (Default = 0) |
|
Enable VCAP overvoltage alarm |
|
Bit 8: |
msk_vout_uv (Default = 0) |
|
Enable VOUT undervoltage alarm |
|
Bit 9: |
msk_vout_ov (Default = 0) |
|
Enable VOUT overvoltage alarm |
|
Bit 10: |
msk_iin_oc (Default = 0) |
|
Enable input overcurrent alarm |
|
Bit 11: |
msk_ichg_uc (Default = 0) |
|
Enable charge undercurrent alarm |
|
Bit 12: |
msk_dtemp_cold (Default = 0) |
|
Enable die temperature cold alarm |
|
Bit 13: |
msk_dtemp_hot (Default = 0) |
|
Enable die temperature hot alarm |
|
Bit 14: |
msk_esr_hi (Default = 0) |
|
Enable ESR high alarm |
|
Bit 15: |
msk_cap_lo (Default = 0) |
|
Enable capacitance low alarm |
| |
| msk_mon_status Address: 0x02 (R/W) |
| Mask Monitor Status Register: Writing a one to any bit in this register enables a rising edge of its respective bit in the mon_status register to trigger an SMBALERT. |
|
Bit 0: |
msk_mon_capesr_active (Default = 0) |
|
Set the SMBALERT when there is a rising edge on mon_capesr_active |
|
Bit 1: |
msk_mon_capesr_scheduled (Default = 0) |
|
Set the SMBALERT when there is a rising edge on mon_capesr_scheduled |
|
Bit 2: |
msk_mon_capesr_pending (Default = 0) |
|
Set the SMBALERT when there is a rising edge on mon_capesr_pending |
|
Bit 3: |
msk_mon_cap_done (Default = 0) |
|
Set the SMBALERT when there is a rising edge on mon_cap_done |
|
Bit 4: |
msk_mon_esr_done (Default = 0) |
|
Set the SMBALERT when there is a rising edge on mon_esr_done |
|
Bit 5: |
msk_mon_cap_failed (Default = 0) |
|
Set the SMBALERT when there is a rising edge on mon_cap_failed |
|
Bit 6: |
msk_mon_esr_failed (Default = 0) |
|
Set the SMBALERT when there is a rising edge on mon_esr_failed |
|
Bit 8: |
msk_mon_power_failed (Default = 0) |
|
Set the SMBALERT when there is a rising edge on mon_power_failed |
|
Bit 9: |
msk_mon_power_returned (Default = 0) |
|
Set the SMBALERT when there is a rising edge on mon_power_returned |
| |
| cap_esr_per_CMD Address: 0x04 (R/W) |
|
|
Bits [15:0]: |
cap_esr_per (Default = 0) |
|
Capacitance and ESR Measurement Period: This register sets the period of repeated capacitance and ESR measurements. Each LSB represents 10 seconds. Capacitance and ESR measurements will not repeat if this register is zero. |
| |
| vcapfb_dac_CMD Address: 0x05 (R/W) |
|
|
Bits [3:0]: |
vcapfb_dac (Default = 15) |
|
VCAP Regulation Reference: This register is used to program the capacitor voltage feedback loop's reference voltage. Only bits 3:0 are active. CAPFBREF = 37.5mV * vcapfb_dac + 637.5mV |
| |
| vshunt_CMD Address: 0x06 (R/W) |
|
|
Bits [15:0]: |
vshunt (Default = 14745) |
|
Shunt Voltage Register: This register programs the shunt voltage for each capacitor in the stack. The charger will limit current and the active shunts will shunt current to prevent this voltage from being exceeded. As a capacitor voltage nears this level, the charge current will be reduced. This should be programmed higher than the intended final balanced individual capacitor voltage. Setting this register to 0x0000 disables the shunt. 183.5uV per LSB. |
| |
| cap_uv_lvl_CMD Address: 0x07 (R/W) |
|
|
Bits [15:0]: |
cap_uv_lvl (Default = 0) |
|
Capacitor Undervoltage Level: This is an alarm threshold for each individual capacitor voltage in the stack. If enabled, any capacitor voltage falling below this level will trigger an alarm and an SMBALERT. 183.5uV per LSB. |
| |
| cap_ov_lvl_CMD Address: 0x08 (R/W) |
|
|
Bits [15:0]: |
cap_ov_lvl (Default = 0) |
|
Capacitor Overvoltage Level: This is an alarm threshold for each individual capacitor in the stack. If enabled, any capacitor voltage rising above this level will trigger an alarm and an SMBALERT. 183.5uV per LSB |
| |
| gpi_uv_lvl_CMD Address: 0x09 (R/W) |
|
|
Bits [15:0]: |
gpi_uv_lvl (Default = 0) |
|
General Purpose Input Undervoltage Level: This is an alarm threshold for the GPI pin. If enabled, the voltage falling below this level will trigger an alarm and an SMBALERT. 183.5uV per LSB |
| |
| gpi_ov_lvl_CMD Address: 0x0A (R/W) |
|
|
Bits [15:0]: |
gpi_ov_lvl (Default = 0) |
|
General Purpose Input Overvoltage Level: This is an alarm threshold for the GPI pin. If enabled, the voltage rising above this level will trigger an alarm and an SMBALERT. 183.5uV per LSB |
| |
| vin_uv_lvl_CMD Address: 0x0B (R/W) |
|
|
Bits [15:0]: |
vin_uv_lvl (Default = 0) |
|
VIN Undervoltage Level: This is an alarm threshold for the input voltage. If enabled, the voltage falling below this level will trigger an alarm and an SMBALERT. 2.21mV per LSB |
| |
| vin_ov_lvl_CMD Address: 0x0C (R/W) |
|
|
Bits [15:0]: |
vin_ov_lvl (Default = 0) |
|
VIN Overvoltage Level: This is an alarm threshold for the input voltage. If enabled, the voltage rising above this level will trigger an alarm and an SMBALERT. 2.21mV per LSB |
| |
| vcap_uv_lvl_CMD Address: 0x0D (R/W) |
|
|
Bits [15:0]: |
vcap_uv_lvl (Default = 0) |
|
VCAP Undervoltage Level: This is an alarm threshold for the capacitor stack voltage. If enabled, the voltage falling below this level will trigger an alarm and an SMBALERT. 1.476mV per LSB |
| |
| vcap_ov_lvl_CMD Address: 0x0E (R/W) |
|
|
Bits [15:0]: |
vcap_ov_lvl (Default = 0) |
|
VCAP Overvoltage Level: This is an alarm threshold for the capacitor stack voltage. If enabled, the voltage rising above this level will trigger an alarm and an SMBALERT. 1.476mV per LSB |
| |
| vout_uv_lvl_CMD Address: 0x0F (R/W) |
|
|
Bits [15:0]: |
vout_uv_lvl (Default = 0) |
|
VOUT Undervoltage Level: This is an alarm threshold for the output voltage. If enabled, the voltage falling below this level will trigger an alarm and an SMBALERT. 2.21mV per LSB |
| |
| vout_ov_lvl_CMD Address: 0x10 (R/W) |
|
|
Bits [15:0]: |
vout_ov_lvl (Default = 0) |
|
VOUT Overvoltage Level: This is an alarm threshold for the output voltage. If enabled, the voltage rising above this level will trigger an alarm and an SMBALERT. 2.21mV per LSB |
| |
| iin_oc_lvl_CMD Address: 0x11 (R/W) |
|
|
Bits [15:0]: |
iin_oc_lvl (Default = 0) |
|
Input Overcurrent Level: This is an alarm threshold for the input current. If enabled, the current rising above this level will trigger an alarm and an SMBALERT. 1.983uV/RSNSI per LSB |
| |
| ichg_uc_lvl_CMD Address: 0x12 (R/W) |
|
|
Bits [15:0]: |
ichg_uc_lvl (Default = 0) |
|
Charge Undercurrent Level: This is an alarm threshold for the charge current. If enabled, the current falling below this level will trigger an alarm and an SMBALERT. 1.983uV/RSNSC per LSB |
| |
| dtemp_cold_lvl_CMD Address: 0x13 (R/W) |
|
|
Bits [15:0]: |
dtemp_cold_lvl (Default = 0) |
|
Die Temperature Cold Level: This is an alarm threshold for the die temperature. If enabled, the die temperature falling below this level will trigger an alarm and an SMBALERT. Temperature = 0.028C per LSB - 251.4C |
| |
| dtemp_hot_lvl_CMD Address: 0x14 (R/W) |
|
|
Bits [15:0]: |
dtemp_hot_lvl (Default = 0) |
|
Die Temperature Hot Level: This is an alarm threshold for the die temperature. If enabled, the die temperature rising above this level will trigger an alarm and an SMBALERT. Temperature = 0.028C per LSB - 251.4C |
| |
| esr_hi_lvl_CMD Address: 0x15 (R/W) |
|
|
Bits [15:0]: |
esr_hi_lvl (Default = 0) |
|
ESR High Level: This is an alarm threshold for the measured stack ESR. If enabled, a measurement of stack ESR exceeding this level will trigger an alarm and an SMBALERT. RSNSC/64 per LSB. |
| |
| cap_lo_lvl_CMD Address: 0x16 (R/W) |
|
|
Bits [15:0]: |
cap_lo_lvl (Default = 0) |
|
Capacitance Low Level: This is an alarm threshold for the measured stack capacitance. If enabled, if the measured stack capacitance is less than this level it will trigger an alarm and an SMBALERT. When ctl_cap_scale is set to 1, capacitance is 3.36uF * RT/RTST per LSB. When ctl_cap_scale is set to 0 it is 336uF * RT/RTST per LSB. |
| |
| ctl_reg Address: 0x17 (R/W) |
| Control Register: Several Control Functions are grouped into this register. |
|
Bit 0: |
ctl_strt_capesr (Default = 0) |
|
Begin a capacitance and ESR measurement when possible; this bit clears itself once a cycle begins. |
|
1: start |
|
Bit 1: |
ctl_gpi_buffer_en (Default = 0) |
|
A one in this bit location enables the input buffer on the GPI pin. With a zero in this location the GPI pin is measured without the buffer. |
|
Bit 2: |
ctl_stop_capesr (Default = 0) |
|
Stops an active capacitance/ESR measurement. |
|
1: stop |
|
Bit 3: |
ctl_cap_scale (Default = 0) |
|
Increases capacitor measurement resolution by 100x, this is used when measuring smaller capacitors. |
|
1: small |
|
0: large |
| |
| num_caps_CMD Address: 0x1A (R) |
|
|
Bits [1:0]: |
num_caps |
|
Number of Capacitors. This register shows the state of the CAP_SLCT1, CAP_SLCT0 pins. The value read in this register is the number of capacitors programmed minus one. |
| |
| chrg_status Address: 0x1B (R) |
| Charger Status Register: This register provides real time status information about the state of the charger system. Each bit is active high. |
|
Bit 0: |
chrg_stepdown |
|
The synchronous controller is in step-down mode (charging) |
|
Bit 1: |
chrg_stepup |
|
The synchronous controller is in step-up mode (backup) |
|
Bit 2: |
chrg_cv |
|
The charger is in constant voltage mode |
|
Bit 3: |
chrg_uvlo |
|
The charger is in under voltage lockout |
|
Bit 4: |
chrg_input_ilim |
|
The charger is in input current limit |
|
Bit 5: |
chrg_cappg |
|
The capacitor voltage is above power good threshold |
|
Bit 6: |
chrg_shnt |
|
The capacitor manager is shunting |
|
Bit 7: |
chrg_bal |
|
The capacitor manager is balancing |
|
Bit 8: |
chrg_dis |
|
The charger is temporarily disabled for capacitance measurement |
|
Bit 9: |
chrg_ci |
|
The charger is in constant current mode |
|
Bit 11: |
chrg_pfo |
|
Input voltage is below PFI threshold |
| |
| mon_status Address: 0x1C (R) |
| Monitor Status: This register provides real time status information about the state of the monitoring system. Each bit is active high. |
|
Bit 0: |
mon_capesr_active |
|
Capacitance/ESR measurement is in progress |
|
Bit 1: |
mon_capesr_scheduled |
|
Waiting programmed time to begin a capacitance/ESR measurement |
|
Bit 2: |
mon_capesr_pending |
|
Waiting for satisfactory conditions to begin a capacitance/ESR measurement |
|
Bit 3: |
mon_cap_done |
|
Capacitance measurement has completed |
|
Bit 4: |
mon_esr_done |
|
ESR Measurement has completed |
|
Bit 5: |
mon_cap_failed |
|
The last attempted capacitance measurement was unable to complete |
|
Bit 6: |
mon_esr_failed |
|
The last attempted ESR measurement was unable to complete |
|
Bit 8: |
mon_power_failed |
|
This bit is set when VIN falls below the PFI threshold or the charger is unable to charge. It is cleared only when power returns and the charger is able to charge. |
|
Bit 9: |
mon_power_returned |
|
This bit is set when the input is above the PFI threshold and the charger is able to charge. It is cleared only when mon_power_failed is set. |
| |
| alarm_reg Address: 0x1D (R) |
| Alarms Register: A one in any bit in the register indicates its respective alarm has triggered. All bits are active high. |
|
Bit 0: |
alarm_cap_uv |
|
Capacitor undervoltage alarm |
|
Bit 1: |
alarm_cap_ov |
|
Capacitor overvoltage alarm |
|
Bit 2: |
alarm_gpi_uv |
|
GPI undervoltage alarm |
|
Bit 3: |
alarm_gpi_ov |
|
GPI overvoltage alarm |
|
Bit 4: |
alarm_vin_uv |
|
VIN undervoltage alarm |
|
Bit 5: |
alarm_vin_ov |
|
VIN overvoltage alarm |
|
Bit 6: |
alarm_vcap_uv |
|
VCAP undervoltage alarm |
|
Bit 7: |
alarm_vcap_ov |
|
VCAP overvoltage alarm |
|
Bit 8: |
alarm_vout_uv |
|
VOUT undervoltage alarm |
|
Bit 9: |
alarm_vout_ov |
|
VOUT overvoltage alarm |
|
Bit 10: |
alarm_iin_oc |
|
Input overcurrent alarm |
|
Bit 11: |
alarm_ichg_uc |
|
Charge undercurrent alarm |
|
Bit 12: |
alarm_dtemp_cold |
|
Die temperature cold alarm |
|
Bit 13: |
alarm_dtemp_hot |
|
Die temperature hot alarm |
|
Bit 14: |
alarm_esr_hi |
|
ESR high alarm |
|
Bit 15: |
alarm_cap_lo |
|
Capacitance low alarm |
| |
| meas_cap_CMD Address: 0x1E (R) |
|
|
Bits [15:0]: |
meas_cap |
|
Measured capacitor stack capacitance value. When ctl_cap_scale is set to 1, capacitance is 3.36uF * RT/RTST per LSB. When ctl_cap_scale is set to 0 it is 336uF * RT/RTST per LSB. |
| |
| meas_esr_CMD Address: 0x1F (R) |
|
|
Bits [15:0]: |
meas_esr |
|
Measured capacitor stack equivalent series resistance (ESR) value. RSNSC/64 per LSB |
| |
| meas_vcap1_CMD Address: 0x20 (R) |
|
|
Bits [15:0]: |
meas_vcap1 |
|
Measured voltage between the CAP1 and CAPRTN pins. 183.5uV per LSB |
| |
| meas_vcap2_CMD Address: 0x21 (R) |
|
|
Bits [15:0]: |
meas_vcap2 |
|
Measured voltage between the CAP2 and CAP1 pins. 183.5uV per LSB |
| |
| meas_vcap3_CMD Address: 0x22 (R) |
|
|
Bits [15:0]: |
meas_vcap3 |
|
Measured voltage between the CAP3 and CAP2 pins. 183.5uV per LSB |
| |
| meas_vcap4_CMD Address: 0x23 (R) |
|
|
Bits [15:0]: |
meas_vcap4 |
|
Measured voltage between the CAP4 and CAP3 pins. 183.5uV per LSB |
| |
| meas_gpi_CMD Address: 0x24 (R) |
|
|
Bits [15:0]: |
meas_gpi |
|
Measurement of GPI pin voltage. 183.5uV per LSB |
| |
| meas_vin_CMD Address: 0x25 (R) |
|
|
Bits [15:0]: |
meas_vin |
|
Measured Input Voltage. 2.21mV per LSB |
| |
| meas_vcap_CMD Address: 0x26 (R) |
|
|
Bits [15:0]: |
meas_vcap |
|
Measured Capacitor Stack Voltage. 1.476mV per LSB. |
| |
| meas_vout_CMD Address: 0x27 (R) |
|
|
Bits [15:0]: |
meas_vout |
|
Measured Output Voltage. 2.21mV per LSB. |
| |
| meas_iin_CMD Address: 0x28 (R) |
|
|
Bits [15:0]: |
meas_iin |
|
Measured Input Current. 1.983uV/RSNSI per LSB |
| |
| meas_ichg_CMD Address: 0x29 (R) |
|
|
Bits [15:0]: |
meas_ichg |
|
Measured Charge Current. 1.983uV/RSNSC per LSB |
| |
| meas_dtemp_CMD Address: 0x2A (R) |
|
|
Bits [15:0]: |
meas_dtemp |
|
Measured die temperature. Temperature = 0.028C per LSB - 251.4C |