| MAXREFDES82# Code Documentation V01.00 Maxim Smart Force Sensor

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system_stm32f4xx.c
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1
66 #include "stm32f4xx.h"
67
68 #if !defined (HSE_VALUE)
69 #define HSE_VALUE ((uint32_t)8000000)
70 #endif /* HSE_VALUE */
71
72 #if !defined (HSI_VALUE)
73 #define HSI_VALUE ((uint32_t)16000000)
74 #endif /* HSI_VALUE */
75
92 /************************* Miscellaneous Configuration ************************/
93
96 /* #define VECT_TAB_SRAM */
97 #define VECT_TAB_OFFSET 0x00
99 /******************************************************************************/
100
116 /* This variable is updated in three ways:
117 1) by calling CMSIS function SystemCoreClockUpdate()
118 2) by calling HAL API function HAL_RCC_GetHCLKFreq()
119 3) each time HAL_RCC_ClockConfig() is called to configure the system clock frequency
120 Note: If you use this function to configure the system clock; then there
121 is no need to call the 2 first functions listed above, since SystemCoreClock
122 variable is updated automatically.
123 */
124 uint32_t SystemCoreClock = 16000000;
125 __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
126
150 void SystemInit(void)
151 {
152 /* FPU settings ------------------------------------------------------------*/
153 #if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
154 SCB->CPACR |= ((3UL << 10*2)|(3UL << 11*2)); /* set CP10 and CP11 Full Access */
155 #endif
156 /* Reset the RCC clock configuration to the default reset state ------------*/
157 /* Set HSION bit */
158 RCC->CR |= (uint32_t)0x00000001;
159
160 /* Reset CFGR register */
161 RCC->CFGR = 0x00000000;
162
163 /* Reset HSEON, CSSON and PLLON bits */
164 RCC->CR &= (uint32_t)0xFEF6FFFF;
165
166 /* Reset PLLCFGR register */
167 RCC->PLLCFGR = 0x24003010;
168
169 /* Reset HSEBYP bit */
170 RCC->CR &= (uint32_t)0xFFFBFFFF;
171
172 /* Disable all interrupts */
173 RCC->CIR = 0x00000000;
174
175 /* Configure the Vector Table location add offset address ------------------*/
176 #ifdef VECT_TAB_SRAM
177 SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
178 #else
179 SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
180 #endif
181 }
182
219 void SystemCoreClockUpdate(void)
220 {
221 uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
222
223 /* Get SYSCLK source -------------------------------------------------------*/
224 tmp = RCC->CFGR & RCC_CFGR_SWS;
225
226 switch (tmp)
227 {
228 case 0x00: /* HSI used as system clock source */
229 SystemCoreClock = HSI_VALUE;
230 break;
231 case 0x04: /* HSE used as system clock source */
232 SystemCoreClock = HSE_VALUE;
233 break;
234 case 0x08: /* PLL used as system clock source */
235
236 /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
237 SYSCLK = PLL_VCO / PLL_P
238 */
239 pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
240 pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
241
242 if (pllsource != 0)
243 {
244 /* HSE used as PLL clock source */
245 pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
246 }
247 else
248 {
249 /* HSI used as PLL clock source */
250 pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
251 }
252
253 pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
254 SystemCoreClock = pllvco/pllp;
255 break;
256 default:
257 SystemCoreClock = HSI_VALUE;
258 break;
259 }
260 /* Compute HCLK frequency --------------------------------------------------*/
261 /* Get HCLK prescaler */
262 tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
263 /* HCLK frequency */
264 SystemCoreClock >>= tmp;
265 }
266
278 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/